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Design and Characterization of RF-LDMOS Transistors and Si-on-SiC Hybrid Substrates
Uppsala University, Disciplinary Domain of Science and Technology, Technology, Department of Engineering Sciences, Solid State Electronics.
2014 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

With increasing amount of user data and applications in wireless communication technology, demands are growing on performance and fabrication costs. One way to decrease cost is to integrate the building blocks in an RF system where digital blocks and high power amplifiers then are combined on one chip. This thesis presents LDMOS transistors integrated in a 65 nm CMOS process without adding extra process steps or masks. High power performance of the LDMOS is demonstrated for an integrated WLAN-PA design at 2.45 GHz with 32.8 dBm output power and measurements also showed that high output power is achievable at 5.8 GHz. For the first time, this kind of device is moreover demonstrated at X-band with over 300 mW/mm output power, targeting communication and radar systems at 8 GHz. As SOI is increasing in popularity due to better device performance and RF benefits, the buried oxide can cause thermal problems, especially for high power devices. To deal with self-heating effects and decrease the RF substrate losses further, this thesis presents a hybrid substrate consisting of silicon on top of polycrystalline silicon carbide (Si-on-poly-SiC). This hybrid substrate utilizes the high thermal conductivity of poly-SiC to reduce device self-heating and the semi-insulating properties to reduce RF losses. Hybrid substrates were successfully fabricated for the first time in 150 mm wafer size by wafer bonding and evaluation was performed in terms of both electrical and thermal measurements and compared to a SOI reference. Successful LDMOS transistors were fabricated for the first time on this type of hybrid substrate where no degradation in electrical performance was seen comparing the LDMOS to identical transistors on the SOI reference. Measurements on calibrated resistors showed that the thermal conductivity was 2.5 times better for the hybrid substrate compared to the SOI substrate. Moreover, RF performance of the hybrid substrate was investigated and the semi-insulating property of poly-SiC showed to be beneficial in achieving a high equivalent substrate parallel resistance and thereby low substrate losses. In a transistor this would be equal to better efficiency and output power. In terms of integration, the hybrid substrate also opens up the possibility of heterogeneous integration where silicon devices and GaN devices can be fabricated on the same chip.

Place, publisher, year, edition, pages
Uppsala: Acta Universitatis Upsaliensis, 2014. , 58 p.
Series
Digital Comprehensive Summaries of Uppsala Dissertations from the Faculty of Science and Technology, ISSN 1651-6214 ; 1113
Keyword [en]
LDMOS, RF, losses, crosstalk, silicon carbide, Si-on-SiC hybrid substrate, wafer bonding, CMOS
National Category
Engineering and Technology Other Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Engineering Science with specialization in Electronics
Identifiers
URN: urn:nbn:se:uu:diva-215390ISBN: 978-91-554-8852-9 (print)OAI: oai:DiVA.org:uu-215390DiVA: diva2:687718
Public defence
2014-02-28, Häggsalen, Ångströmlaboratoriet, Lägerhyddsvägen 1, Uppsala, 09:30 (English)
Opponent
Supervisors
Available from: 2014-02-07 Created: 2014-01-13 Last updated: 2014-02-10
List of papers
1. A +32.8 dBm LDMOS power amplifier for WLAN in 65 nm CMOS technology
Open this publication in new window or tab >>A +32.8 dBm LDMOS power amplifier for WLAN in 65 nm CMOS technology
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2013 (English)In: 2013 8th European Microwave Integrated Circuits Conference Proceedings, 2013, 53-56 p.Conference paper, Oral presentation with published abstract (Refereed)
Abstract [en]

Generating high output power at radio frequencies in CMOS becomes more challenging as technology is scaled. Limitations mainly come from device design. We demonstrate the feasibility of an 10 V LDMOS device fabricated in 65 nm foundry CMOS technology with no added process steps or mask. DC, RF, and power characterization are presented which show the feasibility of the device. The LDMOS device is used in an integrated WLAN-PA design and 32.8 dBm linear output power in the 2.45 GHz band is achieved. Load-pull data also shows high output power capability at 5.8 GHz. The concept can also be used at 45 nm and 28 nm nodes in most foundry CMOS processes.

National Category
Engineering and Technology
Research subject
Engineering Science with specialization in Electronics
Identifiers
urn:nbn:se:uu:diva-209603 (URN)978-2-87487-032-3 (ISBN)
Conference
European Microwave Integrated Circuits Conference (EuMIC)
Available from: 2013-10-22 Created: 2013-10-22 Last updated: 2014-02-10Bibliographically approved
2. Power Performance of 65 nm CMOS Integrated LDMOS Transistors at WLAN and X-band Frequencies
Open this publication in new window or tab >>Power Performance of 65 nm CMOS Integrated LDMOS Transistors at WLAN and X-band Frequencies
2016 (English)In: International journal of microwave and wireless technologies, ISSN 1759-0795, E-ISSN 1759-0787, Vol. 8, no 2, 135-141 p.Article in journal (Refereed) Published
Abstract [en]

Laterally diffused metal oxide semiconductor (LDMOS) transistors with 10V breakdown voltage have been implemented in a 65nm Complementary metal oxide semiconductor (CMOS) process without extra masks or process steps. Radio frequency (RF) performance for Wireless local area network (WLAN) frequencies and in X-band at 8GHz is investigated by load-pull measurements in class AB operation for both 3.3 and 5V supply voltage. Results at 2.45GHz showed 290mW/mm output power density with 17dB linear gain and over 45% power added efficiency (PAE) at 4dB compression at a supply voltage of 5V. Furthermore, results in X-band at 8GHz show 8dB linear gain, 320mW/mm output power density and over 22% PAE at 4dB compression. Third-order intermodulation measurements at 8GHz revealed OIP3 of 18.9 and 21.9dBm at 3.3 and 5V, respectively. The transistors were also tested for reliability which showed no drift in quiescent current after 26h of DC stress while high-power RF stress showed only small extrapolated drift at 10 years in output power density. This is to the authors' knowledge the first time high output power density in X-band is demonstrated for integrated LDMOS transistors manufactured in a 65nm CMOS process without extra process steps.

National Category
Communication Systems
Research subject
Engineering Science with specialization in Electronics
Identifiers
urn:nbn:se:uu:diva-215334 (URN)10.1017/S1759078714001603 (DOI)000370689000002 ()
Available from: 2014-01-13 Created: 2014-01-13 Last updated: 2017-12-06Bibliographically approved
3. Investigating reliability and stress mechanisms of DC and large-signal stressed CMOS 65-nm RF-LDMOS by gate current characterization
Open this publication in new window or tab >>Investigating reliability and stress mechanisms of DC and large-signal stressed CMOS 65-nm RF-LDMOS by gate current characterization
2015 (English)In: IEEE transactions on device and materials reliability, ISSN 1530-4388, E-ISSN 1558-2574, Vol. 15, no 2, 191-197 p.Article in journal (Refereed) Published
Abstract [en]

This paper presents reliability measurements under DC and large-signal conditions of an LDMOS transistor integrated in a 65 nm CMOS process. The gate current was measured with high resolution across the whole operation area with an atto-sense unit, and distinct behavior was seen in the gate current characteristics due to hot-carrier injection (HCI) and Fowler-Nordheim (FN) tunneling. Several bias points were chosen for DC stress of the transistor and degradation of important parameters in terms of RF operation were studied. Furthermore, the behavior from DC stress was compared to large-signal stress of the device in class AB where output power was monitored. Results show that operation at a supply voltage of 3.3 V shows no significant drift of transistor parameters while operation at 5 V shows increase in on-resistance but no changes in quiescent current or threshold voltage. These results are in coherence with what DC stress at quiescent bias points for class AB showed and may imply that DC stress measurements are sufficient in order to understand transistor reliability during RF operation.

National Category
Physical Sciences Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Engineering Science with specialization in Electronics
Identifiers
urn:nbn:se:uu:diva-215335 (URN)10.1109/TDMR.2015.2413845 (DOI)000356174400009 ()
Available from: 2014-01-13 Created: 2014-01-13 Last updated: 2017-12-06Bibliographically approved
4. Fabrication and Characterization of 150 mm Silicon-on-polycrystalline-Silicon Carbide Substrates
Open this publication in new window or tab >>Fabrication and Characterization of 150 mm Silicon-on-polycrystalline-Silicon Carbide Substrates
Show others...
2012 (English)In: Journal of Electronic Materials, ISSN 0361-5235, E-ISSN 1543-186X, Vol. 41, no 3, 480-487 p.Article in journal (Refereed) Published
Abstract [en]

Silicon-on-insulator (SOI) substrates can reduce RF-substrate losses due to their buried oxide (BOX). On the other hand, the BOX causes problems since it acts as a thermal barrier. Oxide has low thermal conductivity and traps the heat that is generated in devices on the SOI. This paper presents a hybrid substrate which uses a thin layer of poly-crystalline silicon and poly-crystalline silicon carbide (Si-on-poly-SiC) to replace the thermally unfavorable buried oxide and the silicon substrate. 150 mm substrates were fabricated by wafer bonding and shown to be stress and strain free. Various electronic devices and test structures were processed on the hybrid substrate as well as on a low resistivity SOI reference wafer. The substrates were characterized electrically and thermally and compared to each other. Results showed that the Si-on-poly-SiC wafer had a 2.5 times lower thermal resistance and was equally or better in electrical performance compared to the SOI reference wafer.

National Category
Engineering and Technology Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Engineering Science with specialization in Electronics
Identifiers
urn:nbn:se:uu:diva-162180 (URN)10.1007/s11664-011-1827-2 (DOI)000299930100009 ()
Available from: 2011-12-12 Created: 2011-11-25 Last updated: 2017-12-08Bibliographically approved
5. LDMOS-transistors on semi-insulating silicon-on-polycrystalline-silicon carbide substrates for improved RF and thermal properties
Open this publication in new window or tab >>LDMOS-transistors on semi-insulating silicon-on-polycrystalline-silicon carbide substrates for improved RF and thermal properties
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2012 (English)In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 70, 14-19 p.Article in journal (Refereed) Published
Abstract [en]

SOI enables reduced capacitive coupling in RF power technology but the thick oxide causes thermal problems. In this paper, the authors present a new type of substrate, where the oxide insulator and the silicon substrate in SOI, are replaced by silicon carbide (SiC). SiC has higher thermal conductivity and is semi-insulating which can improve the thermal and RF performance. Here, LDMOS-transistors are processed and characterized on 150 mm silicon-on-polycrystalline-silicon carbide (Si-on-poly-SiC) substrates as well as on high power and RF optimized SOI reference substrates. The electrical performance for the Si-on-poly-SiC was improved or equal compared to the SOI reference and the device self-heating was reduced. The hybrid substrate had lower RF losses and the RF measurements on transistors were not ideal due to no isolation between the devices.

National Category
Engineering and Technology Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Engineering Science with specialization in Electronics
Identifiers
urn:nbn:se:uu:diva-162179 (URN)10.1016/j.sse.2011.11.019 (DOI)000302494500004 ()
Conference
EUROSOI 2011 Conference, 17-19 January 2011, Granada Andalucia.
Available from: 2011-12-08 Created: 2011-11-25 Last updated: 2017-12-08Bibliographically approved
6. RF losses, crosstalk and temperature dependence for SOI and Si/SiC hybrid substrates
Open this publication in new window or tab >>RF losses, crosstalk and temperature dependence for SOI and Si/SiC hybrid substrates
2014 (English)In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 97, 59-65 p.Article in journal (Refereed) Published
Abstract [en]

Single- and polycrystalline silicon carbide (6H-SiC/poly-SiC) substrates were investigated regarding RF losses and crosstalk for their use in Si/SiC hybrid substrates. Such hybrid substrates would be ideal for silicon high power and high frequency applications. To get a relevant comparison to SOI substrates, silicon substrates with varying resistivity were also included in the study. Regarding the crosstalk, both 6H-SiC and poly-SiC are capacitive across the whole frequency range, and the level of crosstalk is dependent on geometry and frequency. The low resistivity (LR) silicon substrate shows low crosstalk compared to medium and high resistivity (MR/HR) substrates, which both suffer from high crosstalk due to the substrate resistivity and dielectric relaxation effects in the GHz range. From 1-port measurements of RF losses it was observed that 6H-SiC by far has the lowest losses. The poly-SiC has low losses in the same range as the LR substrate while the MR substrate showed the highest losses. The 6H-SiC and LR silicon substrates were unaffected at higher temperatures, while at these conditions, HR silicon behaves more like MR silicon. Overall, the poly-SiC substrate has complex behavior with frequency dependent components, but still has the advantages necessary for successful realization of low loss Si/SiC hybrid substrates.

National Category
Engineering and Technology Other Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Engineering Science with specialization in Electronics
Identifiers
urn:nbn:se:uu:diva-210617 (URN)10.1016/j.sse.2014.04.030 (DOI)000337873200010 ()
Available from: 2013-11-12 Created: 2013-11-12 Last updated: 2017-12-06Bibliographically approved

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