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Extending statistical cache models to support detailed pipeline simulators
Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems. (UART)
Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems. (UART)
Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems. (UART)
2014 (English)In: 2014 IEEE International Symposium On Performance Analysis Of Systems And Software (Ispass), IEEE Computer Society, 2014, 86-95 p.Conference paper, Published paper (Refereed)
Abstract [en]

Simulators are widely used in computer architecture research. While detailed cycle-accurate simulations provide useful insights, studies using modern workloads typically require days or weeks. Evaluating many design points, only exacerbates the simulation overhead. Recent works propose methods with good accuracy that reduce the simulated overhead either by sampling the execution (e.g., SMARTS and SimPoint) or by using fast analytical models of the simulated designs (e.g., Interval Simulation). While these techniques reduce significantly the simulation overhead, modeling processor components with large state, such as the last-level cache, requires costly simulation to warm them up. Statistical simulation methods, such as SMARTS, report that the warm-up overhead accounts for 99% of the simulation overhead, while only 1% of the time is spent simulating the target design. This paper proposes WarmSim, a method that eliminates the need to warm up the cache. WarmSim builds on top of a statistical cache modeling technique and extends it to model accurately not only the miss ratio but also the outcome of every cache request. WarmSim uses as input, an application's memory reuse information which is hardware independent. Therefore, different cache configurations can be simulated using the same input data. We demonstrate that this approach can be used to estimate the CPI of the SPEC CPU2006 benchmarks with an average error of 1.77%, reducing the overhead compared to a simulation with a 10M instruction warm-up by a factor of 50x.

Place, publisher, year, edition, pages
IEEE Computer Society, 2014. 86-95 p.
Series
IEEE International Symposium on Performance Analysis of Systems and Software-ISPASS
National Category
Computer Science
Identifiers
URN: urn:nbn:se:uu:diva-224221DOI: 10.1109/ISPASS.2014.6844464ISI: 000364102000010ISBN: 978-1-4799-3604-5 (print)OAI: oai:DiVA.org:uu-224221DiVA: diva2:715851
Conference
ISPASS 2014, March 23-25, Monterey, CA
Projects
UPMARC
Available from: 2014-05-06 Created: 2014-05-06 Last updated: 2016-01-26Bibliographically approved

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Nikoleris, NikosEklöv, DavidHagersten, Erik

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