Managing power constraints in a single-core scenario through power tokens
2014 (English)In: Journal of Supercomputing, ISSN 0920-8542, E-ISSN 1573-0484, Vol. 68, no 1, 414-442 p.Article in journal (Refereed) Published
Current microprocessors face constant thermal and power-related problems during their everyday use, usually solved by applying a power budget to the processor/core. Dynamic voltage and frequency scaling (DVFS) has been an effective technique that allowed microprocessors to match a predefined power budget. However, the continuous increase of leakage power due to technology scaling along with low resolution of DVFS makes it less attractive as a technique to match a predefined power budget as technology goes to deep-submicron. In this paper, we propose the use of microarchitectural techniques to accurately match a power constraint while maximizing the energy-efficiency of the processor. We will predict the processor power dissipation at cycle level (power token throttling) or at a basic block level (basic block level mechanism), using the dissipated power translated into tokens to select between different power-saving microarchitectural techniques. We also introduce a two-level approach in which DVFS acts as a coarse-grain technique to lower the average power dissipation towards the power budget, while microarchitectural techniques focus on removing the numerous power spikes. Experimental results show that the use of power-saving microarchitectural techniques in conjunction with DVFS is up to six times more precise, in terms of total energy consumed over the power budget, than only using DVFS to match a predefined power budget.
Place, publisher, year, edition, pages
2014. Vol. 68, no 1, 414-442 p.
Hardware, Power management, Power budget, DVFS, Energy efficiency, Power estimation
IdentifiersURN: urn:nbn:se:uu:diva-225084DOI: 10.1007/s11227-013-1044-2ISI: 000334577000016OAI: oai:DiVA.org:uu-225084DiVA: diva2:724967