uu.seUppsala University Publications
Change search
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • ieee
  • modern-language-association
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf
A tunable cache for approximate computing
Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems. (UART)
Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems. (UART)
Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems. (UART)
2014 (English)In: Proc. 10th International Symposium on Nanoscale Architectures, Piscataway, NJ: IEEE , 2014, 88-89 p.Conference paper, Published paper (Refereed)
Abstract [en]

CMOS scaling is near its end but new emerging devices are being developed to replace CMOS. These devices have different features than CMOS, such as the possibility for multi-value logic, which present new opportunities when designing computer systems. In this work we investigate the use of multi-value devices to design a cache that can tune the amount of resources used to store application data. We leverage work on approximate computing to store data that are not application critical in a compact quaternary format while critical data is stored in a more error resilient binary format.

Place, publisher, year, edition, pages
Piscataway, NJ: IEEE , 2014. 88-89 p.
Series
IEEE International Symposium on Nanoscale Architectures, ISSN 2327-8218
National Category
Computer Engineering
Identifiers
URN: urn:nbn:se:uu:diva-234419DOI: 10.1109/NANOARCH.2014.6880480ISI: 000346169900017ISBN: 9781479963843 (print)OAI: oai:DiVA.org:uu-234419DiVA: diva2:756629
Conference
EEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) 2014, July 8-10, Paris, France
Projects
TOLOP
Available from: 2014-07-10 Created: 2014-10-17 Last updated: 2016-07-27Bibliographically approved

Open Access in DiVA

No full text

Other links

Publisher's full text

Authority records BETA

Själander, MagnusShariati Nilsson, NinaKaxiras, Stefanos

Search in DiVA

By author/editor
Själander, MagnusShariati Nilsson, NinaKaxiras, Stefanos
By organisation
Computer Systems
Computer Engineering

Search outside of DiVA

GoogleGoogle Scholar

doi
isbn
urn-nbn

Altmetric score

doi
isbn
urn-nbn
Total: 506 hits
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • ieee
  • modern-language-association
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf