A tunable cache for approximate computing
2014 (English)In: Proc. 10th International Symposium on Nanoscale Architectures, Piscataway, NJ: IEEE , 2014, 88-89 p.Conference paper (Refereed)
CMOS scaling is near its end but new emerging devices are being developed to replace CMOS. These devices have different features than CMOS, such as the possibility for multi-value logic, which present new opportunities when designing computer systems. In this work we investigate the use of multi-value devices to design a cache that can tune the amount of resources used to store application data. We leverage work on approximate computing to store data that are not application critical in a compact quaternary format while critical data is stored in a more error resilient binary format.
Place, publisher, year, edition, pages
Piscataway, NJ: IEEE , 2014. 88-89 p.
, IEEE International Symposium on Nanoscale Architectures, ISSN 2327-8218
IdentifiersURN: urn:nbn:se:uu:diva-234419DOI: 10.1109/NANOARCH.2014.6880480ISI: 000346169900017ISBN: 9781479963843OAI: oai:DiVA.org:uu-234419DiVA: diva2:756629
EEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) 2014, July 8-10, Paris, France