A case for resource efficient prefetching in multicores
2014 (English)In: Proc. International Symposium on Performance Analysis of Systems and Software: ISPASS 2014, IEEE Computer Society, 2014, 137-138 p.Conference paper, Poster (Refereed)
Hardware prefetching has proven very effective for hiding memory latency and can speed up some applications by more than 40%. However, this speedup comes at the cost of often prefetching a significant volume of useless data which wastes shared last level cache space and off-chip bandwidth. This directly impacts the performance of co-scheduled applications which compete for shared resources in multicores. This paper explores how a resource-efficient prefetching scheme can benefit performance by conserving shared resources in multicores. We present a framework that uses fast cache modeling to accurately identify memory instructions that benefit most from prefetching. The framework inserts software prefetches in the application only when they benefit performance, and employs cache bypassing whenever possible. These properties help reduce off-chip bandwidth consumption and last-level cache pollution. While single-thread performance remains comparable to hardware prefetching, the full advantage of the scheme is realized when several cores are used and demand for shared resources grows.
Place, publisher, year, edition, pages
IEEE Computer Society, 2014. 137-138 p.
IdentifiersURN: urn:nbn:se:uu:diva-234546DOI: 10.1109/ISPASS.2014.6844473ISBN: 978-1-4799-3604-5OAI: oai:DiVA.org:uu-234546DiVA: diva2:757003
ISPASS 2014, March 23-25, Monterey, CA