A case for resource efficient prefetching in multicores
2014 (English)In: Proc. 43rd International Conference on Parallel Processing, IEEE Computer Society, 2014, 101-110 p.Conference paper (Refereed)
Modern processors typically employ sophisticated prefetching techniques for hiding memory latency. Hardware prefetching has proven very effective and can speed up some SPEC CPU 2006 benchmarks by more than 40% when running in isolation. However, this speedup often comes at the cost of prefetching a significant volume of useless data (sometimes more than twice the data required) which wastes shared last level cache space and off-chip bandwidth. This paper explores how an accurate resource-efficient prefetching scheme can benefit performance by conserving shared resources in multicores. We present a framework that uses low-overhead runtime sampling and fast cache modeling to accurately identify memory instructions that frequently miss in the cache. We then use this information to automatically insert software prefetches in the application. Our prefetching scheme has good accuracy and employs cache bypassing whenever possible. These properties help reduce off-chip bandwidth consumption and last-level cache pollution. While single-thread performance remains comparable to hardware prefetching, the full advantage of the scheme is realized when several cores are used and demand for shared resources grows. We evaluate our method on two modern commodity multicores. Across 180 mixed workloads that fully utilize a multicore, the proposed software prefetching mechanism achieves up to 24% better throughput than hardware prefetching, and performs 10% better on average.
Place, publisher, year, edition, pages
IEEE Computer Society, 2014. 101-110 p.
IdentifiersURN: urn:nbn:se:uu:diva-234547DOI: 10.1109/ICPP.2014.19ISBN: 978-1-4799-5618-0OAI: oai:DiVA.org:uu-234547DiVA: diva2:757009
2014 43nd International Conference on Parallel Processing (ICPP), September 9-12, Minneapolis, MN