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Modeling cache coherence misses on multicores
Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
2014 (English)In: 2014 IEEE INTERNATIONAL SYMPOSIUM ON PERFORMANCE ANALYSIS OF SYSTEMS AND SOFTWARE (ISPASS), IEEE, 2014, 96-105 p.Conference paper, Published paper (Refereed)
Abstract [en]

While maintaining the coherency of private caches, invalidation-based cache coherence protocols introduce cache coherence misses. We address the problem of predicting the number of cache coherence misses in the private cache of a parallel application when running on a multicore system with an invalidation-based cache coherence protocol. We propose three new performance models (uniform, phased and symmetric) for estimating the number of coherence misses from information about inter-core data sharing patterns and the individual core's data reuse patterns. The inputs to the uniform and phased models are the write frequency and reuse distance distribution of shared data from different cores. This input can be obtained either from profiling the target application on a single core or by analyzing the data access pattern statically, and does not need a detailed simulation of the pattern of interleaving accesses to shared data. The output of the models is an estimated number of coherence misses of the target application. The output can be combined with the number of other kinds of misses to estimate the total number of misses in each core's private cache. This output can also be used to guide program optimization to improve cache performance. We evaluate our models with a set of benchmarks from the PARSEC benchmark suite on real hardware.

Place, publisher, year, edition, pages
IEEE, 2014. 96-105 p.
Series
IEEE International Symposium on Performance Analysis of Systems and Software-ISPASS
National Category
Computer Systems
Research subject
Computer Science
Identifiers
URN: urn:nbn:se:uu:diva-238139DOI: 10.1109/ISPASS.2014.6844465ISI: 000364102000011ISBN: 978-1-4799-3604-5 (print)OAI: oai:DiVA.org:uu-238139DiVA: diva2:770104
Conference
2014 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), Monterey, CA
Projects
UPMARC
Available from: 2014-12-09 Created: 2014-12-09 Last updated: 2016-02-22Bibliographically approved
In thesis
1. Performance Modeling of Multi-core Systems: Caches and Locks
Open this publication in new window or tab >>Performance Modeling of Multi-core Systems: Caches and Locks
2016 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

Performance is an important aspect of computer systems since it directly affects user experience. One way to analyze and predict performance is via performance modeling. In recent years, multi-core systems have made processors more powerful while keeping power consumption relatively low. However the complicated design of these systems makes it difficult to analyze performance. This thesis presents performance modeling techniques for cache performance and synchronization cost on multi-core systems.

A cache can be designed in many ways with different configuration parameters including cache size, associativity and replacement policy. Understanding cache performance under different configurations is useful to explore the design choices. We propose a general modeling framework for estimating the cache miss ratio under different cache configurations, based on the reuse distance distribution. On multi-core systems, each core usually has a private cache. Keeping shared data in private caches coherent has an extra cost. We propose three models to estimate this cost, based on information that can be gathered when running the program on a single core.

Locks are widely used as a synchronization primitive in multi-threaded programs on multi-core systems. While they are often necessary for protecting shared data, they also introduce lock contention, which causes performance issues. We present a model to predict how much contention a lock has on multi-core systems, based on information obtainable from profiling a run on a single core. If lock contention is shown to be a performance bottleneck, one of the ways to mitigate it is to use another lock implementation. However, it is costly to investigate if adopting another lock implementation would reduce lock contention since it requires reimplementation and measurement. We present a model for forecasting lock contention with another lock implementation without replacing the current lock implementation.

Place, publisher, year, edition, pages
Uppsala: Acta Universitatis Upsaliensis, 2016. 55 p.
Series
Digital Comprehensive Summaries of Uppsala Dissertations from the Faculty of Science and Technology, ISSN 1651-6214 ; 1336
Keyword
performance modeling, performance analysis, multi-core, cache, lock
National Category
Computer Science
Identifiers
urn:nbn:se:uu:diva-271124 (URN)978-91-554-9451-3 (ISBN)
Public defence
2016-03-07, 2446, ITC, Lägerhyddsvägen 2, Uppsala, 13:15 (English)
Opponent
Supervisors
Available from: 2016-02-19 Created: 2016-01-05 Last updated: 2016-03-09Bibliographically approved

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Pan, XiaoyueJonsson, Bengt

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