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Verification of buffered dynamic register automata
Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
2015 (English)In: Networked Systems: NETYS 2015, Springer, 2015, p. 15-31Conference paper, Published paper (Refereed)
Place, publisher, year, edition, pages
Springer, 2015. p. 15-31
Series
Lecture Notes in Computer Science ; 9466
National Category
Computer Sciences
Identifiers
URN: urn:nbn:se:uu:diva-247828DOI: 10.1007/978-3-319-26850-7_2ISBN: 978-3-319-26849-1 (print)OAI: oai:DiVA.org:uu-247828DiVA, id: diva2:797608
Conference
NETYS 2015, May 13–15, Agadir, Morocco
Projects
ProFuNUPMARC
Funder
Swedish Foundation for Strategic Research , RIT08-0065Available from: 2016-03-23 Created: 2015-03-24 Last updated: 2018-01-11Bibliographically approved
In thesis
1. Verification of networks of communicating processes: Reachability problems and decidability issues
Open this publication in new window or tab >>Verification of networks of communicating processes: Reachability problems and decidability issues
2017 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

Computer systems are used in almost all aspects of our lives and our dependency on them keeps on increasing. When computer systems are used to handle critical tasks, any software failure can cause severe human and/or material losses. Therefore, for such applications, it is important to detect software errors at an early stage of software development. Furthermore, the growing use of concurrent and distributed programs exponentially increases the complexity of computer systems, making the problem of detecting software errors even harder (if not impossible). This calls for defining systematic and efficient techniques to evaluate the safety and the correctness of programs. The aim of Model-Checking is to analyze automatically whether a given program satisfies its specification. Early applications of Model-Checking were restricted to systems whose behaviors can be captured by finite graphs, so called finite-state systems. Since many computer systems cannot be modeled as finite-state machines, there has been a growing interest in extending the applicability of Model-Checking to infinite-state systems.

The goal of this thesis is to extend the applicability of Model Checking for three instances of infinite-state systems: Ad-Hoc Networks, Dynamic Register Automata and Multi Pushdown Systems. Each one of these instances models challenging types of networks of communicating processes. In both Ad-Hoc Networks and Dynamic Register Automata, communication is carried through message passing. In each type of network, a graph topology models the communication links between processes in the network. The graph topology is static in the case of Ad-Hoc Networks while it is dynamic in the case of Dynamic Register Automata. The number of processes in both types of networks is unbounded. Finally, we consider Multi Pushdown Systems, a model used to study the behaviors of concurrent programs composed of sequential recursive sequential programs communicating through a shared memory.

Place, publisher, year, edition, pages
Uppsala: Acta Universitatis Upsaliensis, 2017. p. 148
Series
Digital Comprehensive Summaries of Uppsala Dissertations from the Faculty of Science and Technology, ISSN 1651-6214 ; 1605
Keywords
program verification, model checking, infinite-state systems, distributed programs, concurrent programs, networks of communicating processes, reachability, termination, decidability
National Category
Computer Sciences
Research subject
Computer Science
Identifiers
urn:nbn:se:uu:diva-334788 (URN)978-91-513-0169-3 (ISBN)
Public defence
2018-01-12, ITC/2446, Polacksbacken, Lägerhyddsvägen 2,, Uppsala, 13:15 (English)
Opponent
Supervisors
Available from: 2017-12-21 Created: 2017-11-27 Last updated: 2018-03-08

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Abdulla, Parosh AzizAtig, Mohamed FaouziRezine, Othmane

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