A dual-consistency cache coherence protocol
2015 (English)In: Proc. 29th International Parallel and Distributed Processing Symposium, Los Alamitos, CA: IEEE Computer Society, 2015, 1119-1128 p.Conference paper (Refereed)
Weak memory consistency models can maximize system performance by enabling hardware and compiler optimizations, but increase programming complexity since they do not match programmers’ intuition. The design of an efficient system with an intuitive memory model is an open challenge.
This paper proposes SPEL, a dual-consistency cache coherence protocol which simultaneously guarantees the strongest memory consistency model provided by the hardware and yields improvements in both performance and energy consumption. The design of the protocol exploits a compile-time identification of code regions which can be executed under a less restrictive, thus optimized protocol, without harming correctness. Outside these regions, code is executed under a more restrictive protocol which enforces sequential consistency. Compared to a standard directory protocol, we show improvements in performance of 24% and reductions in energy consumption of 32%, on average, for a 64-core chip multiprocessor.
Place, publisher, year, edition, pages
Los Alamitos, CA: IEEE Computer Society, 2015. 1119-1128 p.
IdentifiersURN: urn:nbn:se:uu:diva-256060DOI: 10.1109/IPDPS.2015.43ISBN: 978-1-4799-8648-4OAI: oai:DiVA.org:uu-256060DiVA: diva2:824439
IPDPS 2015, May 25–29, Hyderabad, India
ProjectsUPMARCVR frame project ”Efficient Modeling of Heterogeneity in the Era of Dark Silicon”: 106201305/C0533201Fundacíon Seneca-Agencia de Ciencia y Tecnología de la Regíon de Murcia under grant ”Jóvenes Líderes en Investigacíon”: 18956/JLI/13