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Optimizing transfers of control in the static pipeline architecture
Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication. (UART)ORCID iD: 0000-0003-4232-6976
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2015 (English)In: Proc. 16th ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems, New York: ACM Press, 2015, 7-16 p.Conference paper (Refereed)
Abstract [en]

Statically pipelined processors offer a new way to improve the performance beyond that of a traditional in-order pipeline while simultaneously reducing energy usage by enabling the compiler to control more fine-grained details of the program execution. This paper describes how a compiler can exploit the features of the static pipeline architecture to apply optimizations on transfers of control that are not possible on a conventional architecture. The optimizations presented in this paper include hoisting the target address calculations for branches, jumps, and calls out of loops, performing branch chaining between calls and jumps, hoisting the setting of return addresses out of loops, and exploiting conditional calls and returns. The benefits of performing these transfer of control optimizations include a 6.8% reduction in execution time and a 3.6% decrease in estimated energy usage.

Place, publisher, year, edition, pages
New York: ACM Press, 2015. 7-16 p.
National Category
Computer Systems
URN: urn:nbn:se:uu:diva-260544DOI: 10.1145/2670529.2754952ISI: 000370875500001ISBN: 978-1-4503-3257-6OAI: oai:DiVA.org:uu-260544DiVA: diva2:847505
LCTES 2015, June 18–19, Portland, OR
Available from: 2015-06-04 Created: 2015-08-20 Last updated: 2016-04-05Bibliographically approved

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Själander, Magnus
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