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Improving data access efficiency by using context-aware loads and stores
Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication. (UART)ORCID iD: 0000-0003-4232-6976
2015 (English)In: Proc. 16th ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems, New York: ACM Press, 2015, 27-36 p.Conference paper (Refereed)
Abstract [en]

Memory operations have a significant impact on both performance and energy usage even when an access hits in the level-one data cache (L1 DC). Load instructions in particular affect performance as they frequently result in stalls since the register to be loaded is often referenced before the data is available in the pipeline. L1 DC accesses also impact energy usage as they typically require significantly more energy than a register file access. Despite their impact on performance and energy usage, L1 DC accesses on most processors are performed in a general fashion without regard to the context in which the load or store operation is performed. We describe a set of techniques where the compiler enhances load and store instructions so that they can be executed with fewer stalls and/or enable the L1 DC to be accessed in a more energy-efficient manner. We show that using these techniques can simultaneously achieve a 6% gain in performance and a 43% reduction in L1 DC energy usage.

Place, publisher, year, edition, pages
New York: ACM Press, 2015. 27-36 p.
Keyword [en]
Algorithms; Measurements; Performance; Energy; Data Caches; Compiler Optimizations
National Category
Computer Systems
URN: urn:nbn:se:uu:diva-260543DOI: 10.1145/2670529.2754960ISI: 000370875500003ISBN: 978-1-4503-3257-6OAI: oai:DiVA.org:uu-260543DiVA: diva2:847509
LCTES 2015, June 18–19, Portland, OR
Swedish Research Council, 2009-4566
Available from: 2015-06-04 Created: 2015-08-20 Last updated: 2016-04-05Bibliographically approved

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Själander, Magnus
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