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An efficient, self-contained, on-chip directory: DIR1-SISD
Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication. (UART)
(UART)
Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication. (UART)
Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication. (UART)
2015 (English)In: Proc. 24th International Conference on Parallel Architectures and Compilation Techniques, IEEE Computer Society, 2015, 317-330 p.Conference paper, Published paper (Refereed)
Place, publisher, year, edition, pages
IEEE Computer Society, 2015. 317-330 p.
National Category
Computer Systems
Identifiers
URN: urn:nbn:se:uu:diva-265611DOI: 10.1109/PACT.2015.23ISI: 000378942700027ISBN: 978-1-4673-9524-3 (print)OAI: oai:DiVA.org:uu-265611DiVA: diva2:866338
Conference
PACT 2015, October 18–21, San Francisco, CA
Available from: 2015-11-02 Created: 2015-11-02 Last updated: 2017-04-22Bibliographically approved
In thesis
1. Advances Towards Data-Race-Free Cache Coherence Through Data Classification
Open this publication in new window or tab >>Advances Towards Data-Race-Free Cache Coherence Through Data Classification
2017 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

Providing a consistent view of the shared memory based on precise and well-defined semantics—memory consistency model—has been an enabling factor in the widespread acceptance and commercial success of shared-memory architectures. Moreover, cache coherence protocols have been employed by the hardware to remove from the programmers the burden of dealing with the memory inconsistency that emerges in the presence of the private caches. The principle behind all such cache coherence protocols is to guarantee that consistent values are read from the private caches at all times.

In its most stringent form, a cache coherence protocol eagerly enforces two invariants before each data modification: i) no other core has a copy of the data in its private caches, and ii) all other cores know where to receive the consistent data should they need the data later. Nevertheless, by partly transferring the responsibility for maintaining those invariants to the programmers, commercial multicores have adopted weaker memory consistency models, namely the Total Store Order (TSO), in order to optimize the performance for more common cases.

Moreover, memory models with more relaxed invariants have been proposed based on the observation that more and more software is written in compliance with the Data-Race-Free (DRF) semantics. The semantics of DRF software can be leveraged by the hardware to infer when data in the private caches might be inconsistent. As a result, hardware ignores the inconsistent data and retrieves the consistent data from the shared memory. DRF semantics therefore removes from the hardware the burden of eagerly enforcing the strong consistency invariants before each data modification. Instead, consistency is guaranteed only when needed. This results in manifold optimizations, such as reducing the energy consumption and improving the performance and scalability. The efficiency of detecting and discarding the inconsistent data is an important factor affecting the efficiency of such coherence protocols. For instance, discarding the consistent data does not affect the correctness, but results in performance loss and increased energy consumption.

In this thesis we show how data classification can be leveraged as an effective tool to simplify the cache coherence based on the DRF semantics. In particular, we introduce simple but efficient hardware-based private/shared data classification techniques that can be used to efficiently detect the inconsistent data, thus enabling low-overhead and scalable cache coherence solutions based on the DRF semantics.

Place, publisher, year, edition, pages
Uppsala: Acta Universitatis Upsaliensis, 2017. 64 p.
Series
Digital Comprehensive Summaries of Uppsala Dissertations from the Faculty of Science and Technology, ISSN 1651-6214 ; 1521
Keyword
Shared Memory Architectures, Multicore, Memory Hierarchy, Cache Coherence, Data Classification
National Category
Computer Systems
Identifiers
urn:nbn:se:uu:diva-320595 (URN)978-91-554-9925-9 (ISBN)
Public defence
2017-06-08, 2446, Lägerhyddsvägen 2, Hus 2, Uppsala, 13:15 (English)
Opponent
Supervisors
Available from: 2017-05-15 Created: 2017-04-22 Last updated: 2017-05-17

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Davari, MahdadRos, AlbertoHagersten, ErikKaxiras, Stefanos

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