Performance Modeling of Multi-core Systems: Caches and Locks
2016 (English)Doctoral thesis, comprehensive summary (Other academic)
Performance is an important aspect of computer systems since it directly affects user experience. One way to analyze and predict performance is via performance modeling. In recent years, multi-core systems have made processors more powerful while keeping power consumption relatively low. However the complicated design of these systems makes it difficult to analyze performance. This thesis presents performance modeling techniques for cache performance and synchronization cost on multi-core systems.
A cache can be designed in many ways with different configuration parameters including cache size, associativity and replacement policy. Understanding cache performance under different configurations is useful to explore the design choices. We propose a general modeling framework for estimating the cache miss ratio under different cache configurations, based on the reuse distance distribution. On multi-core systems, each core usually has a private cache. Keeping shared data in private caches coherent has an extra cost. We propose three models to estimate this cost, based on information that can be gathered when running the program on a single core.
Locks are widely used as a synchronization primitive in multi-threaded programs on multi-core systems. While they are often necessary for protecting shared data, they also introduce lock contention, which causes performance issues. We present a model to predict how much contention a lock has on multi-core systems, based on information obtainable from profiling a run on a single core. If lock contention is shown to be a performance bottleneck, one of the ways to mitigate it is to use another lock implementation. However, it is costly to investigate if adopting another lock implementation would reduce lock contention since it requires reimplementation and measurement. We present a model for forecasting lock contention with another lock implementation without replacing the current lock implementation.
Place, publisher, year, edition, pages
Uppsala: Acta Universitatis Upsaliensis, 2016. , 55 p.
Digital Comprehensive Summaries of Uppsala Dissertations from the Faculty of Science and Technology, ISSN 1651-6214 ; 1336
performance modeling, performance analysis, multi-core, cache, lock
IdentifiersURN: urn:nbn:se:uu:diva-271124ISBN: 978-91-554-9451-3OAI: oai:DiVA.org:uu-271124DiVA: diva2:891196
2016-03-07, 2446, ITC, Lägerhyddsvägen 2, Uppsala, 13:15 (English)
Whalley, David, Professor
Jonsson, Bengt, Professor
List of papers