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Verification of Cache Coherence Protocols wrt. Trace Filters
Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
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2015 (English)In: Proc. 15th Conference on Formal Methods in Computer-Aided Design, Piscataway, NJ: IEEE , 2015, p. 9-16Conference paper, Published paper (Refereed)
Place, publisher, year, edition, pages
Piscataway, NJ: IEEE , 2015. p. 9-16
National Category
Computer Sciences
Identifiers
URN: urn:nbn:se:uu:diva-272322ISBN: 978-0-9835678-5-1 (print)OAI: oai:DiVA.org:uu-272322DiVA, id: diva2:893648
Conference
FMCAD 2015, September 27–30, Austin, TX
Projects
UPMARC
Available from: 2015-09-30 Created: 2016-01-13 Last updated: 2018-04-09
In thesis
1. Caches, Transactions and Memories: Models, Coherence and Consistency
Open this publication in new window or tab >>Caches, Transactions and Memories: Models, Coherence and Consistency
2018 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

Computers have brought us inestimable convenience in recent years. We have become dependent on them and more sensitive to their performance. During the past decades, we have been trying to improve program efficiency. The invention of multi-core systems is regarded as the new era of boosting performance of computer programs. When we focus on improving program efficiency, we also need to pay attention to program correctness. In some specific areas, errors, aka bugs, of programs can cause disastrous consequences. The dominant approach to bug detection is testing, which is conducted by executing a program against test cases generated based on scenarios. A bug is found when the output of the program does not match the expected output defined in the test case. One main drawback of testing is that it only shows the presence of bugs. An alternative approach is formal verification, which is a method that can exhaustively analyze the program executions and therefore show the absence of bugs. This thesis focuses on one of the main areas of formal verification - model checking. Model checking analyzes a mathematical model extracted from a program and automatically checks if it satisfies the desired properties.

In this thesis, we first consider verifying safety and liveness properties for transactional memories. In particular, we consider the FlexTM hybrid transactional memory. We build a formal model of FlexTM, and apply a small model theorem that restricts the number of threads and variables in the model. This allows us to reduce the problem of verifying safety and liveness properties of FlexTM to checking language inclusion between the automata of FlexTM and a reference transactional memory. Second, we present a method for automatic verification of cache coherence protocols in the presence of transactional memories. We build a formal model containing a filter that represents the conflict resolution strategies of the transactional memory. We also apply a small model theorem which limits the number of cache lines of the protocol. To check cache coherence, we extend a backward reachability algorithm for infinite state systems, by removing the traces not allowed by the filter. Using this technique, we verify two cache protocols under different transactional memories respectively and conclude that they both maintain coherence.  Finally, we consider verification of safety properties of programs running over Self-Invalidate and Self-Downgrade cache coherence protocols. To that end, we define a formal model which captures the weak memory model induced by such protocols. We design an algorithm for inserting a set of optimal fences in the program, which guarantees the safety property while still maintaining the efficiency of a maximal degree.

Place, publisher, year, edition, pages
Uppsala: Acta Universitatis Upsaliensis, 2018. p. 83
Series
Digital Comprehensive Summaries of Uppsala Dissertations from the Faculty of Science and Technology, ISSN 1651-6214 ; 1665
Keyword
cache coherence protocol, transactional memory, weak memory model, model checking, parameterized system
National Category
Computer Sciences
Research subject
Computer Science
Identifiers
urn:nbn:se:uu:diva-347787 (URN)978-91-513-0321-5 (ISBN)
Public defence
2018-05-30, ITC/2446, Lägerhyddsvägen 2, Uppsala, 09:00 (English)
Opponent
Supervisors
Available from: 2018-05-08 Created: 2018-04-09 Last updated: 2018-05-08

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Abdulla, Parosh AzizAtig, Mohamed FaouziZhu, Yunyun

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