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Stateless model checking for POWER
Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
2016 (English)In: Computer Aided Verification: Part II, Springer, 2016, 134-156 p.Conference paper (Refereed)
Place, publisher, year, edition, pages
Springer, 2016. 134-156 p.
Series
, Lecture Notes in Computer Science, 9780
National Category
Computer Science
Identifiers
URN: urn:nbn:se:uu:diva-295424DOI: 10.1007/978-3-319-41540-6_8ISBN: 978-3-319-41539-0OAI: oai:DiVA.org:uu-295424DiVA: diva2:933649
Conference
CAV 2016, July 17–23, Toronto, Canada
Projects
UPMARC
Available from: 2016-07-13 Created: 2016-06-07 Last updated: 2016-08-22Bibliographically approved
In thesis
1. Verification of Software under Relaxed Memory
Open this publication in new window or tab >>Verification of Software under Relaxed Memory
2016 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

The work covered in this thesis concerns automatic analysis of correctness of parallel programs running under relaxed memory models.

When a parallel program is compiled and executed on a modern architecture, various optimizations may cause it to behave in unexpected ways. In particular, accesses to the shared memory may appear in the execution in the opposite order to how they appear in the control flow of the original program source code. The memory model determines which memory accesses can be reordered in a program on a given system. Any memory model that allows some observable memory access reordering is called a relaxed memory model. The reorderings may cause bugs and make the production of parallel programs more difficult.

In this work, we consider three main approaches to analysis of correctness of programs running under relaxed memory models. An exact analysis for finite state programs running under the TSO memory model (Paper I). This technique is based on the well quasi ordering framework. An over-approximate analysis for integer programs running under TSO (Paper II), based on predicate abstraction combined with a buffer abstraction. Two under-approximate analysis techniques for programs running under the TSO, PSO or POWER memory models (Papers III and IV). The latter two techniques are based on stateless model checking and dynamic partial order reduction.

In addition to determining whether a program is correct under a given memory model, the problem of automatic fence synthesis is also considered. A memory fence is an instruction that can be inserted into a program in order to locally disable some memory access reorderings. The fence synthesis problem is the problem of automatically inferring a minimal set of memory fences which restores sufficient order in a given program to ensure its correctness.

Place, publisher, year, edition, pages
Uppsala: Acta Universitatis Upsaliensis, 2016. 102 p.
Series
Digital Comprehensive Summaries of Uppsala Dissertations from the Faculty of Science and Technology, ISSN 1651-6214 ; 1387
Keyword
verification, relaxed memory models
National Category
Computer Science
Research subject
Computer Science
Identifiers
urn:nbn:se:uu:diva-297201 (URN)978-91-554-9616-6 (ISBN)
External cooperation:
Public defence
2016-09-07, 2446, Polacksbacken, Lägerhyddsvägen 2, Uppsala, 13:15 (English)
Opponent
Supervisors
Projects
UPMARC
Available from: 2016-08-17 Created: 2016-06-22 Last updated: 2016-08-25

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