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Cache memory behavior of advanced PDE solvers
Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems. (Uppsala Architecture Research Team)
Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Division of Scientific Computing. Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Numerical Analysis. (Software Aspects of High-Performance Computing)
Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Division of Scientific Computing. Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Numerical Analysis.
2004 (English)In: Parallel Computing: Software Technology, Algorithms, Architectures and Applications, Amsterdam, The Netherlands: Elsevier , 2004, 475-482 p.Conference paper, Published paper (Refereed)
Place, publisher, year, edition, pages
Amsterdam, The Netherlands: Elsevier , 2004. 475-482 p.
Series
Advances in Parallel Computing, 13
National Category
Computer Science Computational Mathematics
Identifiers
URN: urn:nbn:se:uu:diva-67857ISBN: 0-444-51689-1 (print)OAI: oai:DiVA.org:uu-67857DiVA: diva2:95768
Available from: 2006-05-17 Created: 2006-05-17 Last updated: 2011-11-26Bibliographically approved
In thesis
1. Methods for Creating and Exploiting Data Locality
Open this publication in new window or tab >>Methods for Creating and Exploiting Data Locality
2006 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

The gap between processor speed and memory latency has led to the use of caches in the memory systems of modern computers. Programs must use the caches efficiently and exploit data locality for maximum performance. Multiprocessors, built from many processing units, are becoming commonplace not only in large servers but also in smaller systems such as personal computers. Multiprocessors require careful data locality optimizations since accesses from other processors can lead to invalidations and false sharing cache misses. This thesis explores hardware and software approaches for creating and exploiting temporal and spatial locality in multiprocessors.

We propose the capacity prefetching technique, which efficiently reduces the number of cache misses but avoids false sharing by distinguishing between cache lines involved in communication from non-communicating cache lines at run-time. Prefetching techniques often lead to increased coherence and data traffic. The new bundling technique avoids one of these drawbacks and reduces the coherence traffic in multiprocessor prefetchers. This is especially important in snoop-based systems where the coherence bandwidth is a scarce resource.

Most of the studies have been performed on advanced scientific algorithms. This thesis demonstrates that a cc-NUMA multiprocessor, with hardware data migration and replication optimizations, efficiently exploits the temporal locality in such codes. We further present a method of parallelizing a multigrid Gauss-Seidel partial differential equation solver, which creates temporal locality at the expense of increased communication. Our conclusion is that on modern chip multiprocessors, it is more important to optimize algorithms for data locality than to avoid communication, since communication can take place using a shared cache.

Place, publisher, year, edition, pages
Uppsala: Acta Universitatis Upsaliensis, 2006. 37 p.
Series
Digital Comprehensive Summaries of Uppsala Dissertations from the Faculty of Science and Technology, ISSN 1651-6214 ; 176
Keyword
data locality, temporal locality, spatial locality, prefetching, cache, cache behavior, cache coherence, snooping protocols, partial differential equation, shared-memory multiprocessor, chip multiprocessor, simulation
National Category
Computer Engineering
Identifiers
urn:nbn:se:uu:diva-6837 (URN)91-554-6555-2 (ISBN)
Public defence
2006-05-24, Room 2446, Polacksbacken, Lägerhyddsvägen 2D, Uppsala, 13:15 (English)
Opponent
Supervisors
Available from: 2006-04-28 Created: 2006-04-28 Last updated: 2011-02-18Bibliographically approved

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Wallin, DanJohansson, HenrikHolmgren, Sverker

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