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  • 1.
    Abdulla, Parosh Aziz
    et al.
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
    Atig, Mohamed Faouzi
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
    Kaxiras, Stefanos
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication.
    Leonardsson, Carl
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
    Ros, Alberto
    Zhu, Yunyun
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
    Fencing programs with self-invalidation and self-downgrade2016In: Formal Techniques for Distributed Objects, Components, and Systems, Springer, 2016, p. 19-35Conference paper (Refereed)
  • 2.
    Abdulla, Parosh Aziz
    et al.
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
    Atig, Mohamed Faouzi
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
    Kaxiras, Stefanos
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication.
    Leonardsson, Carl
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
    Ros, Alberto
    Zhu, Yunyun
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
    Mending fences with self-invalidation and self-downgrade2018In: Logical Methods in Computer Science, ISSN 1860-5974, E-ISSN 1860-5974, Vol. 14, no 1, article id 6Article in journal (Refereed)
  • 3.
    Alipour, Mehdi
    et al.
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication.
    Carlson, Trevor E.
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication.
    Kaxiras, Stefanos
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication.
    Exploring the performance limits of out-of-order commit2017In: Proc. 14th Computing Frontiers Conference, New York: ACM Press, 2017, p. 211-220Conference paper (Refereed)
  • 4.
    Alirezaie, Marjan
    et al.
    Örebro University.
    Renoux, Jennifer
    Örebro University.
    Köckemann, Uwe
    Örebro University.
    Kristoffersson, Annica
    Örebro University.
    Karlsson, Lars
    Örebro University.
    Blomqvist, Eva
    SICS East.
    Tsiftes, Nicolas
    SICS.
    Voigt, Thiemo
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication. SICS.
    Loutfi, Amy
    Örebro University.
    An Ontology-based Context-aware System for Smart Homes: E-care@ home2017In: Sensors, ISSN 1424-8220, E-ISSN 1424-8220, Vol. 17, no 7Article in journal (Refereed)
  • 5. Alonso, Juan M.
    et al.
    Nordhamn, Amanda
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication.
    Olofsson, Simon
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication.
    Voigt, Thiemo
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication.
    Bounds on the lifetime of wireless sensor networks with lossy links and directional antennas2016In: Wireless Network Performance Enhancement via Directional Antennas: Models, Protocols, and Systems, Boca Raton, FL: CRC Press, 2016, p. 329-361Chapter in book (Refereed)
  • 6.
    Alves, Ricardo
    et al.
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication.
    Nikoleris, Nikos
    Kaxiras, Stefanos
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication.
    Black-Schaffer, David
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication.
    Addressing energy challenges in filter caches2017In: Proc. 29th International Symposium on Computer Architecture and High Performance Computing, IEEE Computer Society, 2017, p. 49-56Conference paper (Refereed)
  • 7.
    Asan, Noor Badariah
    et al.
    Uppsala University, Disciplinary Domain of Science and Technology, Technology, Department of Engineering Sciences, Solid State Electronics. Universiti Teknikal Malaysia Melaka, Melaka Malaysia.
    Carlos, Pérez Penichet
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication.
    Redzwan, Syaiful
    Uppsala University, Disciplinary Domain of Science and Technology, Technology, Department of Engineering Sciences, Solid State Electronics.
    Noreland, Daniel
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology.
    Hassan, Emadeldeen
    Umeå University.
    Rydberg, Anders
    Uppsala University, Disciplinary Domain of Science and Technology, Technology, Department of Engineering Sciences, Solid State Electronics.
    Blokhuis, Taco
    Maastricht University Medical Center+, Netherlands.
    Voigt, Thiemo
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication.
    Augustine, Robin
    Uppsala University, Disciplinary Domain of Science and Technology, Technology, Department of Engineering Sciences, Solid State Electronics.
    Data Packet Transmission through Fat Tissue for Wireless Intra-Body Networks2017In: IEEE Journal of Electromagnetics, RF and Microwaves in Medicine and Biology, ISSN 2469-7249Article in journal (Refereed)
    Abstract [en]

    This work explores high data rate microwave communication through fat tissue in order to address the wide bandwidth requirements of intra-body area networks. We have designed and carried out experiments on an IEEE 802.15.4 based WBAN prototype by measuring the performance of the fat tissue channel in terms of data packet reception with respect to tissue length and power transmission. This paper proposes and demonstrates a high data rate communication channel through fat tissue using phantom and ex-vivo environments. Here, we achieve a data packet reception of approximately 96 % in both environments. The results also show that the received signal strength drops by ~1 dBm per 10 mm in phantom and ~2 dBm per 10 mm in ex-vivo. The phantom and ex-vivo experimentations validated our approach for high data rate communication through fat tissue for intrabody network applications. The proposed method opens up new opportunities for further research in fat channel communication. This study will contribute to the successful development of high bandwidth wireless intra-body networks that support high data rate implanted, ingested, injected, or worn devices

  • 8.
    Asan, Noor Badariah
    et al.
    Uppsala University, Disciplinary Domain of Science and Technology, Technology, Department of Engineering Sciences, Solid State Electronics.
    Noreland, Daniel
    Hassan, Emadeldeen
    Redzwan, Syaiful
    Uppsala University, Disciplinary Domain of Science and Technology, Technology, Department of Engineering Sciences, Solid State Electronics.
    Rydberg, Anders
    Uppsala University, Disciplinary Domain of Science and Technology, Technology, Department of Engineering Sciences, Solid State Electronics.
    Blokhuis, Taco J.
    Carlsson, Per-Ola
    Voigt, Thiemo
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication.
    Augustine, Robin
    Uppsala University, Disciplinary Domain of Science and Technology, Technology, Department of Engineering Sciences, Solid State Electronics.
    Intra-body microwave communication through adipose tissue2017In: Healthcare Technology Letters, E-ISSN 2053-3713, Vol. 4, no 4, p. 115-121Article in journal (Refereed)
  • 9.
    Asan, Noor Badariah
    et al.
    Uppsala University, Disciplinary Domain of Science and Technology, Technology, Department of Engineering Sciences, Solid State Electronics.
    Redzwan, Syaiful
    Uppsala University, Disciplinary Domain of Science and Technology, Technology, Department of Engineering Sciences, Solid State Electronics.
    Rydberg, Anders
    Uppsala University, Disciplinary Domain of Science and Technology, Technology, Department of Engineering Sciences, Solid State Electronics.
    Augustine, Robin
    Uppsala University, Disciplinary Domain of Science and Technology, Technology, Department of Engineering Sciences, Solid State Electronics.
    Noreland, Daniel
    Hassan, Emadeldeen
    Voigt, Thiemo
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication.
    Human fat tissue: A microwave communication channel2017In: Proc. 1st MTT-S International Microwave Bio Conference, IEEE, 2017Conference paper (Refereed)
    Abstract [en]

    In this paper, we present an approach for communication through human body tissue in the R-band frequency range. This study examines the ranges of microwave frequencies suitable for intra-body communication. The human body tissues are characterized with respect to their transmission properties using simulation modeling and phantom measurements. The variations in signal coupling with respect to different tissue thicknesses are studied. The simulation and phantom measurement results show that electromagnetic communication in the fat layer is viable with attenuation of approximately 2 dB per 20 mm. 

  • 10.
    Asan, Noor Badariah
    et al.
    Uppsala University, Disciplinary Domain of Science and Technology, Technology, Department of Engineering Sciences, Solid State Electronics.
    Velander, Jacob
    Uppsala University, Disciplinary Domain of Science and Technology, Technology, Department of Engineering Sciences, Solid State Electronics.
    Redzwan, Syaiful
    Uppsala University, Disciplinary Domain of Science and Technology, Technology, Department of Engineering Sciences, Solid State Electronics.
    Augustine, Robin
    Uppsala University, Disciplinary Domain of Science and Technology, Technology, Department of Engineering Sciences, Solid State Electronics.
    Hassan, Emadeldeen
    Department of Computing Science, Umeå University, Umeå, Sweden.
    Noreland, Daniel
    Department of Computing Science, Umeå University, Umeå, Sweden.
    Voigt, Thiemo
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication.
    Blokhuis, Taco J.
    Department of Surgery, Maastricht University Medical Center+, Maastricht, The Netherland.
    Reliability of the fat tissue channel for intra-body microwave communication2017In: 2017 IEEE Conference on Antenna Measurements & Applications (CAMA), IEEE, 2017, p. 310-313Conference paper (Refereed)
    Abstract [en]

    Recently, the human fat tissue has been proposed as a microwave channel for intra-body sensor applications. In this work, we assess how disturbances can prevent reliable microwave propagation through the fat channel. Perturbants of different sizes are considered. The simulation and experimental results show that efficient communication through the fat channel is possible even in the presence of perturbants such as embedded muscle layers and blood vessels. We show that the communication channel is not affected by perturbants that are smaller than 15 mm cube.

  • 11.
    Bagci, Ibrahim Ethem
    et al.
    Univ Lancaster, Sch Comp & Commun, Lancaster, England.
    Raza, Shahid
    SICS Swedish ICT, Kista, Sweden.
    Roedig, Utz
    Univ Lancaster, Sch Comp & Commun, Lancaster, England.
    Voigt, Thiemo
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication. SICS Swedish ICT, Kista, Sweden.
    Fusion: Coalesced Confidential Storage and Communication Framework for the IoT2016In: Security and Communication Networks, ISSN 1939-0114, E-ISSN 1939-0122, Vol. 9, no 15, p. 2656-2673Article in journal (Refereed)
    Abstract [en]

    Comprehensive security mechanisms are required for a successful implementation of the Internet of Things (IoT). Existing solutions focus mainly on securing the communication links between Internet hosts and IoT devices. However, as most IoT devices nowadays provide vast amounts of flash storage space, it is as well required to consider storage security within a comprehensive security framework. Instead of developing independent security solutions for storage and communication, we propose Fusion, a framework that provides coalesced confidential storage and communication. Fusion uses existing secure communication protocols for the IoT such as Internet protocol security (IPsec) and datagram transport layer security (DTLS) and re-uses the defined communication security mechanisms within the storage component. Thus, trusted mechanisms developed for communication security are extended into the storage space. Notably, this mechanism allows us to transmit requested data directly from the file system without decrypting read data blocks and then re-encrypting these for transmission. Thus, Fusion provides benefits in terms of processing speed and energy efficiency, which are important aspects for resource-constrained IoT devices. This paper describes the Fusion architecture and its instantiation for IPsec-based and DTLS-based systems. We describe Fusion's implementation and evaluate its storage overheads, communication performance, and energy consumption.

  • 12. Baird, Ryan
    et al.
    Gavin, Peter
    Själander, Magnus
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication.
    Whalley, David
    Uh, Gang-Ryung
    Optimizing transfers of control in the static pipeline architecture2015In: Proc. 16th ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems, New York: ACM Press, 2015, p. 7-16Conference paper (Refereed)
    Abstract [en]

    Statically pipelined processors offer a new way to improve the performance beyond that of a traditional in-order pipeline while simultaneously reducing energy usage by enabling the compiler to control more fine-grained details of the program execution. This paper describes how a compiler can exploit the features of the static pipeline architecture to apply optimizations on transfers of control that are not possible on a conventional architecture. The optimizations presented in this paper include hoisting the target address calculations for branches, jumps, and calls out of loops, performing branch chaining between calls and jumps, hoisting the setting of return addresses out of loops, and exploiting conditional calls and returns. The benefits of performing these transfer of control optimizations include a 6.8% reduction in execution time and a 3.6% decrease in estimated energy usage.

  • 13. Bardizbanyan, Alen
    et al.
    Själander, Magnus
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication.
    Whalley, David
    Larsson-Edefors, Per
    Improving data access efficiency by using context-aware loads and stores2015In: Proc. 16th ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems, New York: ACM Press, 2015, p. 27-36Conference paper (Refereed)
    Abstract [en]

    Memory operations have a significant impact on both performance and energy usage even when an access hits in the level-one data cache (L1 DC). Load instructions in particular affect performance as they frequently result in stalls since the register to be loaded is often referenced before the data is available in the pipeline. L1 DC accesses also impact energy usage as they typically require significantly more energy than a register file access. Despite their impact on performance and energy usage, L1 DC accesses on most processors are performed in a general fashion without regard to the context in which the load or store operation is performed. We describe a set of techniques where the compiler enhances load and store instructions so that they can be executed with fewer stalls and/or enable the L1 DC to be accessed in a more energy-efficient manner. We show that using these techniques can simultaneously achieve a 6% gain in performance and a 43% reduction in L1 DC energy usage.

  • 14.
    Bor, Martin
    et al.
    Lancaster University.
    Roedig, Utz
    Lancaster University.
    Voigt, Thiemo
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication.
    Alonso, Juan
    Univ. Nac. de Cuyo, Argentina.
    Do LoRa Low-Power Wide-Area Networks Scale?2016Conference paper (Refereed)
    Abstract [en]

    New Internet of Things (IoT) technologies such as LongRange (LoRa) are emerging which enable power ecientwireless communication over very long distances. Devicestypically communicate directly to a sink node which removesthe need of constructing and maintaining a complex multi-hop network. Given the fact that a wide area is coveredand that all devices communicate directly to a few sinknodes a large number of nodes have to share the commu-nication medium. LoRa provides for this reason a rangeof communication options (centre frequency, spreading fac-tor, bandwidth, coding rates) from which a transmitter canchoose. Many combination settings are orthogonal and pro-vide simultaneous collision free communications. Neverthe-less, there is a limit regarding the number of transmitters aLoRa system can support. In this paper we investigate thecapacity limits of LoRa networks. Using experiments wedevelop models describing LoRa communication behaviour.We use these models to parameterise a LoRa simulation tostudy scalability. Our experiments show that a typical smartcity deployment can support 120 nodes per 3.8 ha, which isnot sucient for future IoT deployments. LoRa networkscan scale quite well, however, if they use dynamic commu-nication parameter selection and/or multiple sinks.

  • 15.
    Borgström, Gustaf
    et al.
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication.
    Sembrant, Andreas
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication.
    Black-Schaffer, David
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication.
    Adaptive cache warming for faster simulations2017In: Proc. 9th Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, New York: ACM Press, 2017, article id 1Conference paper (Refereed)
  • 16.
    Cambazoglu, Volkan
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Division of Computer Systems. Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication.
    Protocol, mobility and adversary models for the verification of security2016Licentiate thesis, comprehensive summary (Other academic)
    Abstract [en]

    The increasing heterogeneity of communicating devices, ranging from resource constrained battery driven sensor nodes to multi-core processor computers, challenges protocol design. We examine security and privacy protocols with respect to exterior factors such as users, adversaries, and computing and communication resources; and also interior factors such as the operations, the interactions and the parameters of a protocol.

    Users and adversaries interact with security and privacy protocols, and even affect the outcome of the protocols. We propose user mobility and adversary models to examine how the location privacy of users is affected when they move relative to each other in specific patterns while adversaries with varying strengths try to identify the users based on their historical locations. The location privacy of the users are simulated with the support of the K-Anonymity protection mechanism, the Distortion-based metric, and our models of users' mobility patterns and adversaries' knowledge about users.

    Security and privacy protocols need to operate on various computing and communication resources. Some of these protocols can be adjusted for different situations by changing parameters. A common example is to use longer secret keys in encryption for stronger security. We experiment with the trade-off between the security and the performance of the Fiat–Shamir identification protocol. We pipeline the protocol to increase its utilisation as the communication delay outweighs the computation.

    A mathematical specification based on a formal method leads to a strong proof of security. We use three formal languages with their tool supports in order to model and verify the Secure Hierarchical In-Network Aggregation (SHIA) protocol for Wireless Sensor Networks (WSNs). The three formal languages specialise on cryptographic operations, distributed systems and mobile processes. Finding an appropriate level of abstraction to represent the essential features of the protocol in three formal languages was central.

    List of papers
    1. The impact of trace and adversary models on location privacy provided by K-anonymity
    Open this publication in new window or tab >>The impact of trace and adversary models on location privacy provided by K-anonymity
    2012 (English)In: Proc. 1st Workshop on Measurement, Privacy, and Mobility, New York: ACM Press, 2012, article id 6Conference paper, Published paper (Refereed)
    Place, publisher, year, edition, pages
    New York: ACM Press, 2012
    National Category
    Computer Sciences
    Research subject
    Computer Science with specialization in Computer Communication
    Identifiers
    urn:nbn:se:uu:diva-171581 (URN)10.1145/2181196.2181202 (DOI)978-1-4503-1163-2 (ISBN)
    Conference
    MPM 2012
    Projects
    ProFuNWISENET
    Available from: 2012-04-10 Created: 2012-03-22 Last updated: 2018-01-12Bibliographically approved
    2. Towards adaptive zero-knowledge protocols: A case study with Fiat–Shamir identification protocol
    Open this publication in new window or tab >>Towards adaptive zero-knowledge protocols: A case study with Fiat–Shamir identification protocol
    2013 (English)In: Proc. 9th Swedish National Computer Networking Workshop, 2013, p. 67-70Conference paper, Published paper (Refereed)
    Abstract [en]

    Interactive zero-knowledge protocols are used as identification protocols. The protocols are executed in rounds, with security being increased with every round. This allows for a trade-off between security and performance to adapt the protocol to the requirements of the scenario. We experimentally investigate the Fiat–Shamir identification protocol on machines and networks with different performance characteristics. We find that the delay of the protocol highly depends on network latency and upload bandwidth. Computation time becomes more visible, when the protocol transmits little amount of data via a low latency network. We also experience that the impact of the sizes of the variables on the delay of the protocol is less than the number of rounds', which are interior factors in the protocol.

    National Category
    Computer Sciences
    Research subject
    Computer Science with specialization in Computer Communication
    Identifiers
    urn:nbn:se:uu:diva-201070 (URN)
    Conference
    SNCNW 2013
    Projects
    WISENETProFuN
    Available from: 2013-06-05 Created: 2013-06-05 Last updated: 2018-01-11Bibliographically approved
    3. Modelling and analysing a WSN secure aggregation protocol: A comparison of languages and tool support
    Open this publication in new window or tab >>Modelling and analysing a WSN secure aggregation protocol: A comparison of languages and tool support
    2015 (English)Report (Other academic)
    Series
    Technical report / Department of Information Technology, Uppsala University, ISSN 1404-3203 ; 2015-033
    National Category
    Computer Sciences Communication Systems
    Research subject
    Computer Science with specialization in Computer Communication
    Identifiers
    urn:nbn:se:uu:diva-268453 (URN)
    Projects
    ProFuN
    Funder
    Swedish Foundation for Strategic Research , RIT08-0065
    Available from: 2015-12-03 Created: 2015-12-04 Last updated: 2018-01-10Bibliographically approved
  • 17.
    Cambazoglu, Volkan
    et al.
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication.
    Gutkovas, Ramunas
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computing Science.
    Åman Pohjola, Johannes
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computing Science.
    Victor, Björn
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computing Science.
    Modelling and analysing a WSN secure aggregation protocol: A comparison of languages and tool support2015Report (Other academic)
  • 18.
    Carlos, Perez Penichet
    et al.
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication.
    Hermans, Frederik
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication.
    Varshney, Ambuj
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication.
    Voigt, Thiemo
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication.
    Augmenting IoT networks with backscatter-enabled passive sensor tags2016In: Proceedings of the 3rd Workshop on Hot Topics in Wireless, 2016, p. 23-27Conference paper (Refereed)
    Abstract [en]

    The sensing modalities available in an Internet-of-Things (IoT) network are usually fixed before deployment, when the operator selects a suitable IoT platform. Retrofitting a deployment with additional sensors can be cumbersome, because it requires either modifying the deployed hardware or adding new devices that then have to be maintained. In this paper, we present our vision and work towards passive sensor tags: battery-free devices that allow to augment existing IoT deployments with additional sensing capabilities without the need to modify the existing deployment. Our passive sensor tags use backscatter transmissions to communicate with the deployed network. Crucially, they do this in a way that is compatible with the deployed network's radio protocol, and without the need for additional infrastructure. We present an FPGA-based prototype of a passive sensor tag that can communicate with unmodified 802.15.4 IoT devices. Our initial experiments with the prototype support the feasibility of our approach. We also lay out the next steps towards fully realizing the vision of passive sensor tags.

  • 19.
    Carlson, Trevor E.
    et al.
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication.
    Heirman, Wim
    Intel, ExaSci Lab, Santa Clara, CA USA..
    Allam, Osman
    Univ Ghent, B-9000 Ghent, Belgium..
    Kaxiras, Stefanos
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication.
    Eeckhout, Lieven
    Univ Ghent, B-9000 Ghent, Belgium..
    The Load Slice Core Microarchitecture2015In: 2015 ACM/IEEE 42Nd Annual International Symposium On Computer Architecture (ISCA), 2015, p. 272-284Conference paper (Refereed)
    Abstract [en]

    Driven by the motivation to expose instruction-level parallelism (ILP), microprocessor cores have evolved from simple, in-order pipelines into complex, superscalar out-of-order designs. By extracting ILP, these processors also enable parallel cache and memory operations as a useful side-effect. Today, however, the growing off-chip memory wall and complex cache hierarchies of many-core processors make cache and memory accesses ever more costly. This increases the importance of extracting memory hierarchy parallelism (MHP), while reducing the net impact of more general, yet complex and power-hungry ILP-extraction techniques. In addition, for multi-core processors operating in power- and energy-constrained environments, energy-efficiency has largely replaced single-thread performance as the primary concern. Based on this observation, we propose a core microarchitecture that is aimed squarely at generating parallel accesses to the memory hierarchy while maximizing energy efficiency. The Load Slice Core extends the efficient in-order, stall-on-use core with a second in-order pipeline that enables memory accesses and address-generating instructions to bypass stalled instructions in the main pipeline. Backward program slices containing address-generating instructions leading up to loads and stores are extracted automatically by the hardware, using a novel iterative algorithm that requires no software support or recompilation. On average, the Load Slice Core improves performance over a baseline in-order processor by 53% with overheads of only 15% in area and 22% in power, leading to an increase in energy efficiency (MIPS/Watt) over in-order and out-of-order designs by 43% and over 4.7x, respectively. In addition, for a power- and area-constrained many-core design, the Load Slice Core outperforms both in-order and out-of-order designs, achieving a 53% and 95% higher performance, respectively, thus providing an alternative direction for future many-core processors.

  • 20.
    Carlson, Trevor E.
    et al.
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication.
    Tran, Kim-Anh
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication.
    Jimborean, Alexandra
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication.
    Koukos, Konstantinos
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication.
    Själander, Magnus
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication.
    Kaxiras, Stefanos
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication.
    Transcending hardware limits with software out-of-order processing2017In: IEEE Computer Architecture Letters, ISSN 1556-6056, Vol. 16, no 2, p. 162-165Article in journal (Refereed)
  • 21.
    Ceballos, Germán
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication.
    How to make tasks faster: Revealing the complex interactions of tasks in the memory system2017In: Proc. Companion 8th ACM International Conference on Systems, Programming, Languages, and Applications: Software for Humanity, New York: ACM Press, 2017, p. 1-3Conference paper (Refereed)
  • 22.
    Ceballos, Germán
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Division of Computer Systems. Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication.
    Modeling the interactions between tasks and the memory system2017Licentiate thesis, comprehensive summary (Other academic)
    Abstract [en]

    Making computer systems more energy efficient while obtaining the maximum performance possible is key for future developments in engineering, medicine, entertainment, etc. However it has become a difficult task due to the increasing complexity of hardware and software, and their interactions. For example, developers have to deal with deep, multi-level cache hierarchies on modern CPUs, and keep busy thousands of cores in GPUs, which makes the programming process more difficult.

    To simplify this task, new abstractions and programming models are becoming popular. Their goal is to make applications more scalable and efficient, while still providing the flexibility and portability of old, widely adopted models. One example of this is task-based programming, where simple independent tasks (functions) are delegated to a runtime system which orchestrates their execution. This approach has been successful because the runtime can automatically distribute work across hardware cores and has the potential to minimize data movement and placement (e.g., being aware of the cache hierarchy).

    To build better runtime systems, it is crucial to understand bottlenecks in the performance of current and future multicore systems. In this thesis, we provide fast, accurate and mathematically-sound models and techniques to understand the execution of task-based applications concerning three key aspects: memory behavior (data locality), scheduling, and performance. With these methods, we lay the groundwork for improving runtime system, providing insight into the interplay between the schedule's behavior, data reuse through the cache hierarchy, and the resulting performance.

    List of papers
    1. Shared Resource Sensitivity in Task-Based Runtime Systems
    Open this publication in new window or tab >>Shared Resource Sensitivity in Task-Based Runtime Systems
    2013 (English)In: Proc. 6th Swedish Workshop on Multi-Core Computing, Halmstad University Press, 2013Conference paper, Published paper (Refereed)
    Place, publisher, year, edition, pages
    Halmstad University Press, 2013
    National Category
    Computer Systems
    Identifiers
    urn:nbn:se:uu:diva-212780 (URN)
    Conference
    MCC13, November 25–26, Halmstad, Sweden
    Projects
    Resource Sharing ModelingUPMARC
    Funder
    Swedish Research Council
    Available from: 2013-12-13 Created: 2013-12-13 Last updated: 2018-01-26Bibliographically approved
    2. Formalizing data locality in task parallel applications
    Open this publication in new window or tab >>Formalizing data locality in task parallel applications
    2016 (English)In: Algorithms and Architectures for Parallel Processing, Springer, 2016, p. 43-61Conference paper, Published paper (Refereed)
    Place, publisher, year, edition, pages
    Springer, 2016
    Series
    Lecture Notes in Computer Science, ISSN 0302-9743 ; 10049
    National Category
    Computer Sciences
    Identifiers
    urn:nbn:se:uu:diva-310341 (URN)10.1007/978-3-319-49956-7_4 (DOI)000389797000004 ()978-3-319-49955-0 (ISBN)
    Conference
    ICA3PP 2016, December 14–16, Granada, Spain
    Projects
    UPMARCResource Sharing Modeling
    Funder
    Swedish Foundation for Strategic Research , FFL12-0051
    Available from: 2016-11-19 Created: 2016-12-14 Last updated: 2018-01-26Bibliographically approved
    3. TaskInsight: Understanding task schedules effects on memory and performance
    Open this publication in new window or tab >>TaskInsight: Understanding task schedules effects on memory and performance
    2017 (English)In: Proc. 8th International Workshop on Programming Models and Applications for Multicores and Manycores, New York: ACM Press, 2017, p. 11-20Conference paper, Published paper (Refereed)
    Place, publisher, year, edition, pages
    New York: ACM Press, 2017
    National Category
    Computer Engineering
    Identifiers
    urn:nbn:se:uu:diva-315033 (URN)10.1145/3026937.3026943 (DOI)978-1-4503-4883-6 (ISBN)
    Conference
    PMAM 2017, February 4–8, Austin, TX
    Projects
    UPMARCResource Sharing Modeling
    Funder
    Swedish Research CouncilSwedish Foundation for Strategic Research , FFL12-0051EU, Horizon 2020, 687698
    Available from: 2017-02-04 Created: 2017-02-08 Last updated: 2018-01-26Bibliographically approved
    4. Analyzing performance variation of task schedulers with TaskInsight
    Open this publication in new window or tab >>Analyzing performance variation of task schedulers with TaskInsight
    2018 (English)In: Parallel Computing, ISSN 0167-8191, E-ISSN 1872-7336, Vol. 75, p. 11-27Article in journal (Refereed) Published
    National Category
    Computer Engineering
    Identifiers
    urn:nbn:se:uu:diva-340202 (URN)10.1016/j.parco.2018.02.003 (DOI)
    Projects
    UPMARCResource Sharing Modeling
    Available from: 2018-02-22 Created: 2018-01-26 Last updated: 2018-03-03Bibliographically approved
  • 23.
    Ceballos, Germán
    et al.
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication.
    Black-Schaffer, David
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication.
    Spatial and Temporal Cache Sharing Analysis in Tasks2016Conference paper (Other academic)
    Abstract [en]

    Understanding performance of large scale multicore systems is crucial for getting faster execution times and optimize workload efficiency, but it is becoming harder due to the increased complexity of hardware architectures. Cache sharing is a key component for performance in modern architectures, and it has been the focus of performance analysis tools and techniques in recent years.At the same time, new programming models have been introduced to aid the programmer dealing with the complexity of large scale systems, simplifying the coding process and making applications more scalable regardless of resource sharing. Task-based runtime systems are one example of this that became popular recently.In this work we develop models to tackle performance analysis of shared resources in the task-based context, and for that we study cache sharing both in temporal and spatial ways. In temporal cache sharing, the effect of data reused over time by the tasks executed is modeled to predict different scenarios resulting in a tool called StatTask. In spatial cache sharing, the effect of tasks fighting for the cache at a given point in time through their execution is quantified and used to model their behavior on arbitrary cache sizes.Finally, we explain how these tools set up a unique and solid platform to improve runtime systems schedulers, maximizing performance of execution of large-scale task-based applications.

  • 24.
    Ceballos, Germán
    et al.
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication.
    Grass, Thomas
    Barcelona Supercomputing Center, Spain.
    Black-Schaffer, David
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication.
    Hugo, Andra
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication.
    Characterizing Task Scheduling Performance Based on Data Reuse2016In: Proc. 9th Nordic Workshop on Multi-Core Computing, 2016Conference paper (Refereed)
    Abstract [en]

    Through the past years, several scheduling heuristics were introduced to improve the performance of task-based ap-plications, with schedulers increasingly becoming aware of memory-related bottlenecks such as data locality and cachesharing. However, there are not many useful tools that pro-vide insights to developers about why and where dierentschedulers do better scheduling, and how this is related tothe applications' performance. In this work we present atechnique to characterize dierent task schedulers based onthe analysis of data reuse, providing high-level, quantitativeinformation that can be directly correlated with tasks per-formance variation. This exible insight is key for optimiza-tion in many contexts, including data locality, throughput, memory footprint or even energy eciency.

  • 25.
    Ceballos, Germán
    et al.
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication.
    Grass, Thomas
    Hugo, Andra
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication.
    Black-Schaffer, David
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication.
    Analyzing performance variation of task schedulers with TaskInsight2018In: Parallel Computing, ISSN 0167-8191, E-ISSN 1872-7336, Vol. 75, p. 11-27Article in journal (Refereed)
  • 26.
    Ceballos, Germán
    et al.
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication.
    Grass, Thomas
    Hugo, Andra
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication.
    Black-Schaffer, David
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication.
    TaskInsight: Understanding task schedules effects on memory and performance2017In: Proc. 8th International Workshop on Programming Models and Applications for Multicores and Manycores, New York: ACM Press, 2017, p. 11-20Conference paper (Refereed)
  • 27.
    Ceballos, Germán
    et al.
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication.
    Hagersten, Erik
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication.
    Black-Schaffer, David
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication.
    Formalizing data locality in task parallel applications2016In: Algorithms and Architectures for Parallel Processing, Springer, 2016, p. 43-61Conference paper (Refereed)
  • 28.
    Ceballos, Germán
    et al.
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication.
    Hagersten, Erik
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication.
    Black-Schaffer, David
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication.
    StatTask: Reuse distance analysis for task-based applications2015In: Proc. 7th Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, New York: ACM Press, 2015, p. 1-7Conference paper (Refereed)
    Abstract [en]

    Task-based programming has grown in popularity as it provides programmers with an intuitive abstraction for expressing parallelism, and runtimes with flexibility in scheduling and load-balancing. However, while good tools exist for understanding scheduling and load-balancing, little work has been done to analyze how tasks and schedules interact with the cache hierarchy. This area of investigation is particularly important as achieving good data reuse through complex cache hierarchies is essential for performance on modern systems, and the inherent flexibility of task-based runtimes offers an exciting potential for applying such knowledge to improve scheduling.

    This work presents a new approach to model the interaction between tasks, schedules, and the memory hierarchy. The model analyzes the tasks’ data reuse to predict cache behavior for arbitrary task schedules on different memory hierarchies, and does so from only one profiling run. With this approach we can identify the potential for data reuse between tasks, and which can then be leveraged to improve scheduling. 

  • 29.
    Ceballos, Germán
    et al.
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication.
    Hagersten, Erik
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication.
    Black-Schaffer, David
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication.
    Understanding the interplay between task scheduling, memory and performance2017In: Proc. Companion 8th ACM International Conference on Systems, Programming, Languages, and Applications: Software for Humanity, New York: ACM Press, 2017, p. 21-23Conference paper (Refereed)
  • 30.
    Ceballos, Germán
    et al.
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication.
    Hugo, Andra
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication.
    Hagersten, Erik
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication.
    Black-Schaffer, David
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication.
    Exploring scheduling effects on task performance with TaskInsight2017In: Supercomputing frontiers and innovations, ISSN 2214-3270, E-ISSN 2313-8734, Vol. 4, no 3, p. 91-98Article in journal (Refereed)
  • 31.
    Ceballos, Germán
    et al.
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication.
    Sembrant, Andreas
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication.
    Carlson, Trevor E.
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication.
    Black-Schaffer, David
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication.
    Analyzing Graphics Workloads on Tile-based GPUs2017In: Proc. 20th International Symposium on Workload Characterization, IEEE, 2017Conference paper (Refereed)
  • 32. Cebrián, Juan M.
    et al.
    Fernández-Pascual, Ricardo
    Jimborean, Alexandra
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication.
    Acacio, Manuel E.
    Ros, Alberto
    A dedicated private-shared cache design for scalable multiprocessors2017In: Concurrency and Computation, ISSN 1532-0626, E-ISSN 1532-0634, Vol. 29, no 2, article id e3871Article in journal (Refereed)
  • 33.
    Cojean, Terry
    et al.
    University of Bordeaux.
    Guermouche, Abdou
    University of Bordeaux.
    Hugo, Andra
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication.
    Namyst, Raymond
    University of Bordeaux.
    Wacrenier, Pierre-André
    University of Bordeaux.
    Resource aggregation for task-based CholeskyFactorization on top of heterogeneous machines2016Conference paper (Refereed)
  • 34.
    Davari, Mahdad
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Division of Computer Systems. Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication.
    Advances Towards Data-Race-Free Cache Coherence Through Data Classification2017Doctoral thesis, comprehensive summary (Other academic)
    Abstract [en]

    Providing a consistent view of the shared memory based on precise and well-defined semantics—memory consistency model—has been an enabling factor in the widespread acceptance and commercial success of shared-memory architectures. Moreover, cache coherence protocols have been employed by the hardware to remove from the programmers the burden of dealing with the memory inconsistency that emerges in the presence of the private caches. The principle behind all such cache coherence protocols is to guarantee that consistent values are read from the private caches at all times.

    In its most stringent form, a cache coherence protocol eagerly enforces two invariants before each data modification: i) no other core has a copy of the data in its private caches, and ii) all other cores know where to receive the consistent data should they need the data later. Nevertheless, by partly transferring the responsibility for maintaining those invariants to the programmers, commercial multicores have adopted weaker memory consistency models, namely the Total Store Order (TSO), in order to optimize the performance for more common cases.

    Moreover, memory models with more relaxed invariants have been proposed based on the observation that more and more software is written in compliance with the Data-Race-Free (DRF) semantics. The semantics of DRF software can be leveraged by the hardware to infer when data in the private caches might be inconsistent. As a result, hardware ignores the inconsistent data and retrieves the consistent data from the shared memory. DRF semantics therefore removes from the hardware the burden of eagerly enforcing the strong consistency invariants before each data modification. Instead, consistency is guaranteed only when needed. This results in manifold optimizations, such as reducing the energy consumption and improving the performance and scalability. The efficiency of detecting and discarding the inconsistent data is an important factor affecting the efficiency of such coherence protocols. For instance, discarding the consistent data does not affect the correctness, but results in performance loss and increased energy consumption.

    In this thesis we show how data classification can be leveraged as an effective tool to simplify the cache coherence based on the DRF semantics. In particular, we introduce simple but efficient hardware-based private/shared data classification techniques that can be used to efficiently detect the inconsistent data, thus enabling low-overhead and scalable cache coherence solutions based on the DRF semantics.

    List of papers
    1. Hierarchical private/shared classification: The key to simple and efficient coherence for clustered cache hierarchies
    Open this publication in new window or tab >>Hierarchical private/shared classification: The key to simple and efficient coherence for clustered cache hierarchies
    2015 (English)In: Proc. 21st International Symposium on High Performance Computer Architecture, IEEE Computer Society Digital Library, 2015, p. 186-197Conference paper, Published paper (Refereed)
    Abstract [en]

    Hierarchical clustered cache designs are becoming an appealing alternative for multicores. Grouping cores and their caches in clusters reduces network congestion by localizing traffic among several hierarchical levels, potentially enabling much higher scalability. While such architectures can be formed recursively by replicating a base design pattern, keeping the whole hierarchy coherent requires more effort and consideration. The reason is that, in hierarchical coherence, even basic operations must be recursive. As a consequence, intermediate-level caches behave both as directories and as leaf caches. This leads to an explosion of states, protocol-races, and protocol complexity. While there have been previous efforts to extend directory-based coherence to hierarchical designs their increased complexity and verification cost is a serious impediment to their adoption. We aim to address these concerns by encapsulating all hierarchical complexity in a simple function: that of determining when a data block is shared entirely within a cluster (sub-tree of the hierarchy) and is private from the outside. This allows us to eliminate complex recursive operations that span the hierarchy and instead employ simple coherence mechanisms such as self-invalidation and write-through-now restricted to operate within the cluster where a data block is shared. We examine two inclusivity options and discuss the relation of our approach to the recently proposed Hierarchical-Race-Free (HRF) memory models. Finally, comparisons to a hierarchical directory-based MOESI, VIPS-M, and TokenCMP protocols show that, despite its simplicity our approach results in competitive performance and decreased network traffic.

    Place, publisher, year, edition, pages
    IEEE Computer Society Digital Library, 2015
    National Category
    Computer Systems
    Identifiers
    urn:nbn:se:uu:diva-265651 (URN)10.1109/HPCA.2015.7056032 (DOI)000380564900016 ()9781479989300 (ISBN)
    External cooperation:
    Conference
    HPCA 2015, February 7–11, Burlingame, CA
    Available from: 2015-02-11 Created: 2015-11-02 Last updated: 2017-04-22Bibliographically approved
    2. The effects of granularity and adaptivity on private/shared classification for coherence
    Open this publication in new window or tab >>The effects of granularity and adaptivity on private/shared classification for coherence
    2015 (English)In: ACM Transactions on Architecture and Code Optimization (TACO), ISSN 1544-3566, E-ISSN 1544-3973, Vol. 12, no 3, article id 26Article in journal (Refereed) Published
    Abstract [en]

    Classification of data into private and shared has proven to be a catalyst for techniques to reduce coherence cost, since private data can be taken out of coherence and resources can be concentrated on providing coherence for shared data. In this article, we examine how granularity-page-level versus cache-line level- and adaptivity-going from shared to private-affect the outcome of classification and its final impact on coherence. We create a classification technique, called Generational Classification, and a coherence protocol called Generational Coherence, which treats data as private or shared based on cache-line generations. We compare two coherence protocols based on self-invalidation/self-downgrade with respect to data classification. Our findings are enlightening: (i) Some programs benefit from finer granularity, some benefit further from adaptivity, but some do not benefit from either. (ii) Reducing the amount of shared data has no perceptible impact on coherence misses caused by self-invalidation of shared data, hence no impact on performance. (iii) In contrast, classifying more data as private has implications for protocols that employ write-through as a means of self-downgrade, resulting in network traffic reduction-up to 30%-by reducing write-through traffic.

    National Category
    Computer Systems
    Identifiers
    urn:nbn:se:uu:diva-265580 (URN)10.1145/2790301 (DOI)000363004100001 ()
    Available from: 2015-10-06 Created: 2015-11-02 Last updated: 2017-12-01Bibliographically approved
    3. An efficient, self-contained, on-chip directory: DIR1-SISD
    Open this publication in new window or tab >>An efficient, self-contained, on-chip directory: DIR1-SISD
    2015 (English)In: Proc. 24th International Conference on Parallel Architectures and Compilation Techniques, IEEE Computer Society, 2015, p. 317-330Conference paper, Published paper (Refereed)
    Place, publisher, year, edition, pages
    IEEE Computer Society, 2015
    National Category
    Computer Systems
    Identifiers
    urn:nbn:se:uu:diva-265611 (URN)10.1109/PACT.2015.23 (DOI)000378942700027 ()978-1-4673-9524-3 (ISBN)
    Conference
    PACT 2015, October 18–21, San Francisco, CA
    Available from: 2015-11-02 Created: 2015-11-02 Last updated: 2017-04-22Bibliographically approved
    4. Scope-Aware Classification: Taking the hierarchical private/shared data classification to the next level
    Open this publication in new window or tab >>Scope-Aware Classification: Taking the hierarchical private/shared data classification to the next level
    2017 (English)Report (Other academic)
    Series
    Technical report / Department of Information Technology, Uppsala University, ISSN 1404-3203 ; 2017-008
    National Category
    Computer Systems
    Identifiers
    urn:nbn:se:uu:diva-320324 (URN)
    Available from: 2017-04-27 Created: 2017-04-19 Last updated: 2017-07-03Bibliographically approved
    5. The best of both works: A hybrid data-race-free cache coherence scheme
    Open this publication in new window or tab >>The best of both works: A hybrid data-race-free cache coherence scheme
    2017 (English)Report (Other academic)
    National Category
    Computer Systems
    Identifiers
    urn:nbn:se:uu:diva-320320 (URN)
    Available from: 2017-04-19 Created: 2017-04-19 Last updated: 2017-11-15
  • 35.
    Davari, Mahdad
    et al.
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication.
    Hagersten, Erik
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication.
    Kaxiras, Stefanos
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication.
    Scope-Aware Classification: Taking the hierarchical private/shared data classification to the next level2017Report (Other academic)
  • 36.
    Davari, Mahdad
    et al.
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication.
    Hagersten, Erik
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication.
    Kaxiras, Stefanos
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication.
    The best of both works: A hybrid data-race-free cache coherence scheme2017Report (Other academic)
  • 37.
    Davari, Mahdad
    et al.
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication.
    Ros, Alberto
    Hagersten, Erik
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication.
    Kaxiras, Stefanos
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication.
    An efficient, self-contained, on-chip directory: DIR1-SISD2015In: Proc. 24th International Conference on Parallel Architectures and Compilation Techniques, IEEE Computer Society, 2015, p. 317-330Conference paper (Refereed)
  • 38.
    Davari, Mahdad
    et al.
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication.
    Ros, Alberto
    Hagersten, Erik
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication.
    Kaxiras, Stefanos
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication.
    Effects of Granularity/Adaptivity on Private/Shared Classification for Coherence2015Conference paper (Other academic)
  • 39.
    Davari, Mahdad
    et al.
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication.
    Ros, Alberto
    Hagersten, Erik
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication.
    Kaxiras, Stefanos
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication.
    The effects of granularity and adaptivity on private/shared classification for coherence2015In: ACM Transactions on Architecture and Code Optimization (TACO), ISSN 1544-3566, E-ISSN 1544-3973, Vol. 12, no 3, article id 26Article in journal (Refereed)
    Abstract [en]

    Classification of data into private and shared has proven to be a catalyst for techniques to reduce coherence cost, since private data can be taken out of coherence and resources can be concentrated on providing coherence for shared data. In this article, we examine how granularity-page-level versus cache-line level- and adaptivity-going from shared to private-affect the outcome of classification and its final impact on coherence. We create a classification technique, called Generational Classification, and a coherence protocol called Generational Coherence, which treats data as private or shared based on cache-line generations. We compare two coherence protocols based on self-invalidation/self-downgrade with respect to data classification. Our findings are enlightening: (i) Some programs benefit from finer granularity, some benefit further from adaptivity, but some do not benefit from either. (ii) Reducing the amount of shared data has no perceptible impact on coherence misses caused by self-invalidation of shared data, hence no impact on performance. (iii) In contrast, classifying more data as private has implications for protocols that employ write-through as a means of self-downgrade, resulting in network traffic reduction-up to 30%-by reducing write-through traffic.

  • 40. Davis, Brandon
    et al.
    Baird, Ryan
    Gavin, Peter
    Själander, Magnus
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication.
    Finlayson, Ian
    Rasapour, Farhad
    Cook, Gregory
    Uh, Gang-Ryung
    Whalley, David
    Tyson, Gary
    Scheduling instruction effects for a statically pipelined processor2015In: Proc. International Conference on Compilers, Architectures, and Synthesis for Embedded Systems: CASES 2015, Piscataway, NJ: IEEE Press, 2015, p. 167-176Conference paper (Refereed)
    Abstract [en]

    Statically pipelined processors have a fully exposed datapath where all portions of the pipeline are directly controlled by effects within an instruction, which simplifies hardware and enables a new level of compiler optimizations. This paper describes an effect scheduling strategy to aggressively compact instructions, which has a critical impact on code size and performance. Unique scheduling challenges include more frequent name dependences and fewer renaming opportunities due to static pipeline (SP) registers being dedicated for specific operations. We also realized the SP in a hardware implementation language (VHDL) to evaluate the real energy bene fits. Despite the compiler challenges, we achieve performance, code size, and energy improvements compared to a conventional MIPS processor.

  • 41.
    De Guglielmo, Domenico
    et al.
    Univ. of Pisa.
    Al Nahas, Beshr
    SICS.
    Duquennoy, Simon
    SICS.
    Voigt, Thiemo
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication. SICS, S-16429 Kista, Sweden.
    Anastasi, Giuseppe
    University of Pisa.
    Analysis and experimental evaluation of IEEE 802.15.4e TSCH CSMA-CA Algorithm2017In: IEEE Transactions on Vehicular Technology, ISSN 0018-9545, E-ISSN 1939-9359, Vol. 66, no 2, p. 1573-1588Article in journal (Refereed)
    Abstract [en]

    Time-slotted channel hopping (TSCH) is one of the medium access control (MAC) behavior modes defined in the IEEE 802.15.4e standard. It combines time-slotted access and channel hopping, thus providing predictable latency, energy efficiency, communication reliability, and high network capacity. TSCH provides both dedicated and shared links. The latter is special slots assigned to more than one transmitter, whose concurrent access is regulated by a carrier-sense multiple access with collision avoidance (CSMA-CA) algorithm. In this paper, we develop an analytical model of the TSCH CSMA-CA algorithm to predict the performance experienced by nodes when using shared links. The model allows for deriving a number of metrics, such as delivery probability, packet latency, and energy consumption of nodes. Moreover, it considers the capture effect (CE) that typically occurs in real wireless networks. We validate the model through simulation experiments and measurements in a real testbed. Our results show that the model is very accurate. Furthermore, we found that the CE plays a fundamental role as it can significantly improve the performance experienced by nodes.

  • 42.
    Di Lascio, Elena
    et al.
    Universit`a degli Studi Roma Tre, Italy.
    Varshney, Ambuj
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication.
    Thiemo, Voigt
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication. SICS Swedish ICT, Uppsala, Sweden.
    Pérez-Penichet, Carlos
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication.
    Poster Abstract: LocaLight - A Battery-free PassiveLocalization System Using Visible Light2016Conference paper (Refereed)
    Abstract [en]

    Most existing indoor localization systems are battery-powered and use the changes in Radio Frequency (RF) signals to localize objects. In this paper, we present LocaLight: a battery-free indoor localization system that localizes objects using visible light by tracking the shadow they cast. By sensing a drop in the intensity of ambient light caused by the presence of a shadow, LocaLight localizes the object. Since the position of the shadow can be predicted, it is possible to localize the object in a sensitive area by carefully positioning the light sensors and the overhead lights. Our initial results suggest that LocaLight achieves an accuracy comparable to many of the state-of-the art solutions that use RF.

  • 43.
    Elsts, Atis
    et al.
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computing Science.
    Hassani Bijarbooneh, Farshid
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computing Science.
    Jacobsson, Martin
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication.
    Sagonas, Konstantinos
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computing Science.
    Enabling design of performance-controlled sensor network applications through task allocation and reallocation2015In: Proc. 11th International Conference on Distributed Computing in Sensor Systems, IEEE Computer Society, 2015, p. 248-253Conference paper (Refereed)
    Abstract [en]

    Task Graph (ATaG) is a sensor network application development paradigm where the application is visually described by a graph where the nodes correspond to application-level tasks and edges correspond to dataflows. We extend ATaG with the option to add nonfunctional requirements: constraints on end-to-end delay and packet delivery rate. Setting up these constraints at the design phase naturally leads to enabling run-time assurance at the deployment phase, when the conditions of the constraints are used as network's performance goals. We provide both run-time middleware that checks the conditions of these constraints and a central management unit that dynamically adapts the system by doing task reallocation and putting task copies on redundant nodes. Through extensive simulations we show that the system is efficient enough to enable adaptations within tens of seconds even in large networks.

  • 44.
    Elsts, Atis
    et al.
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computing Science.
    Hassani Bijarbooneh, Farshid
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computing Science.
    Jacobsson, Martin
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication.
    Sagonas, Konstantinos
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computing Science.
    ProFuN TG: A tool for programming and managing performance-aware sensor network applications2015In: IEEE 40th Local Computer Networks Conference Workshops (LCN Workshops), IEEE Computer Society, 2015, p. 751-759Conference paper (Refereed)
    Abstract [en]

    Sensor network macroprogramming methodologiessuch as the Abstract Task Graph hold the promise of enablinghigh-level sensor network application development. However,progress in this area is hampered by the scarcity of tools, andalso because of insufficient focus on developing tool support forprogramming applications aware of performance requirements.

    We present ProFuN TG (Task Graph), a tool for designing sen-sor network applications using task graphs. ProFuN TG providesautomated task mapping, sensor node firmware macrocompila-tion, application simulation, deployment, and runtime mainte-nance capabilities. It allows users to incorporate performancerequirements in the applications, expressed through constraintson task-to-task dataflows. The tool includes middleware that usesan efficient flooding-based protocol to set up tasks in the network,and also enables runtime assurance by keeping track of theconstraint conditions.

    We show that the adaptive task reallocation enabled by ourapproach can significantly increase application reliability whiledecreasing energy consumption: in a network with unreliablelinks, we achieve above 99.89 % task-to-task PDR while keepingthe maximal radio duty cycle around 2.0 %.

  • 45.
    Elsts, Atis
    et al.
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computing Science.
    Hassani Bijarbooneh, Farshid
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computing Science.
    Jacobsson, Martin
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication.
    Sagonas, Konstantinos
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computing Science.
    ProFuN TG: A Tool Using Abstract Task Graphs to Facilitate the Development, Deployment and Maintenance of Wireless Sensor Network Applications2015In: Proc. Poster/Demo Session: 12th European Conference on Wireless Sensor Networks, 2015, p. 19-20Conference paper (Refereed)
    Abstract [en]

    In this demo abstract we present ProFuN TG (Task Graph), a tool for sensor network application development using the data-flow programming paradigm. The tool has support for the whole lifecycle of WSN application: from the initial design of its task graph, task placement on network nodes, execution in a simulated environment, deployment on real hardware, to its automated maintenance through task remapping. ProFuN TG allows to program applications that incorporate quality-of-service requirements, expressed through constraints on task-to-task data flows.

  • 46.
    Elsts, Atis
    et al.
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computing Science.
    Hassani Bijarbooneh, Farshid
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computing Science.
    Jacobsson, Martin
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication.
    Sagonas, Konstantinos
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computing Science.
    ProFuN TG: Programming Sensornets with Task Graphs for Increased Reliability and Energy-Efficiency2015Conference paper (Refereed)
    Abstract [en]

    Sensor network macroprogramming methodologies such as the Abstract Task Graph hold the promise of enabling high-level sensor network application development. However, progress in this area is hampered by the scarcity of tools, and also because of insufficient focus on developing tool support for programming applications aware of performance requirements.

    In this demo we present ProFuN TG (Task Graph), a tool for designing sensor network applications using task graphs. ProFuN TG provides automated task mapping, sensor nodefirmware macrocompilation, application simulation, deployment, and runtime maintenance capabilities. It allows users to incorporate performance requirements in the applications, expressed through constraints on task-to-task dataflows. The tool includes middleware that uses an efficient flooding-based protocol to set up tasks in the network, and also enables runtime assurance by keeping track of the constraint conditions.

    Through task allocation in a way that optimizes an objective function in a model of the network, and adaptive task reallocation in case of link, node, or sensor failures the tool helps to make sensornet applications both more energy-efficient and reliable.

  • 47. Elvitigala, Charitha
    et al.
    Tennakoon, Eranda
    Hamza, Ayyoob
    Lokuge, Yasith
    De Zoysa, Kasun
    Keppitiyagama, Chamath
    Iyer, Venkat
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication.
    Hewage, Kasun
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication.
    Voigt, Thiemo
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication. SICS Swedish ICT, Stockholm, Sweden.
    Towards a sensor system to tame the human elephant conflict2015In: Sensors Applications Symposium (SAS), IEEE, 2015, p. 169-172Conference paper (Refereed)
    Abstract [en]

    The human elephant conflict in Sri Lanka has been a cause of major concern over the past decade. Frequent clashes between wild elephants and villagers have resulted in severe damage to property, as well as loss of lives for both humans and elephants. Competition for space is the primary reason for conflict between humans and elephants. Elephants that escape from the wildlife national parks venture into villages creating destruction in their wake. To prevent such mishaps, a proper system is required to contain and monitor elephants in national parks. In this paper, we describe different approaches to detect elephants and possible ways of monitoring the national wildlife parks. We also elaborate on the advantages and limitations of each approach, and determine what sort of system is needed to tame the human elephant conflict.

  • 48. Enemark, Hans-Jacob
    et al.
    Zhang, Yue
    Dragoni, Nicola
    Orfanidis, Charalampos
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication.
    Energy-efficient fault-tolerant dynamic event region detection in wireless sensor networks2015In: Proc. 81st IEEE Vehicular Technology Conference, IEEE conference proceedings, 2015Conference paper (Refereed)
    Abstract [en]

    Fault-tolerant event detection is fundamental to wireless sensor network applications. Existing approaches usually adopt neighborhood collaboration for better detection accuracy,while need more energy consumption due to communication.Focusing on energy efficiency, this paper makes an improvement to a hybrid algorithm for dynamic event region detection, such asreal-time tracking of chemical leakage regions. Considering the characteristics of the moving away dynamic events, we propose areturn back condition for the hybrid algorithm from distributed neighborhood collaboration, in which a node makes its detection decision based on decisions received from its spatial and temporal neighbors, to local non-communicative decision making. The simulation results demonstrate that the improved algorithm doesnot degrade the detection accuracy of the original algorithm,while it has better energy efficiency with the number of messages exchanged in the network decreased.

  • 49.
    Fafoutis, Xenofon
    et al.
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication.
    Di Mauro, Alessio
    Orfanidis, Charalampos
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication.
    Dragoni, Nicola
    Energy-efficient medium access control for energy harvesting communications2015In: IEEE transactions on consumer electronics, ISSN 0098-3063, E-ISSN 1558-4127, Vol. 61, no 4, p. 402-410Article in journal (Refereed)
    Abstract [en]

    While energy consumption is widely considered the primary challenge of wireless networked devices, energy harvesting emerges as a promising way of powering the Internet of Things (IoT). In the Medium Access Control (MAC) layer of the communication stack, energy harvesting introduces spatial and temporal uncertainty in the availability of energy. In this context, this paper focuses on the design and implementation of the MAC layer of wireless embedded systems that are powered by energy harvesting; providing novel protocol features and practical experiences to designers of consumer electronics who opt for tailoring their own protocol solutions instead of using the standards(1).

  • 50.
    Feeney, Laura Marie
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication.
    Inter-network interactions in the internet-of-things: Protocol and architecture challenges2015Conference paper (Refereed)
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