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  • 1.
    Abdulla, Parosh Aziz
    et al.
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorteknik.
    Atig, Mohamed Faouzi
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorteknik.
    Kaxiras, Stefanos
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    Leonardsson, Carl
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorteknik.
    Ros, Alberto
    Zhu, Yunyun
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorteknik.
    Fencing programs with self-invalidation and self-downgrade2016Ingår i: Formal Techniques for Distributed Objects, Components, and Systems, Springer, 2016, s. 19-35Konferensbidrag (Refereegranskat)
  • 2.
    Abdulla, Parosh Aziz
    et al.
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorteknik.
    Atig, Mohamed Faouzi
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorteknik.
    Kaxiras, Stefanos
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    Leonardsson, Carl
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorteknik.
    Ros, Alberto
    Zhu, Yunyun
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorteknik.
    Mending fences with self-invalidation and self-downgrade2018Ingår i: Logical Methods in Computer Science, ISSN 1860-5974, E-ISSN 1860-5974, Vol. 14, nr 1, artikel-id 6Artikel i tidskrift (Refereegranskat)
  • 3.
    Alipour, Mehdi
    et al.
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    Carlson, Trevor E.
    Black-Schaffer, David
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    Kaxiras, Stefanos
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    Maximizing limited resources: A limit-based study and taxonomy of out-of-order commit2019Ingår i: Journal of Signal Processing Systems, ISSN 1939-8018, E-ISSN 1939-8115, Vol. 91, nr 3-4, s. 379-397Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    Out-of-order execution is essential for high performance, general-purpose computation, as it can find and execute useful work instead of stalling. However, it is typically limited by the requirement of visibly sequential, atomic instruction executionin other words, in-order instruction commit. While in-order commit has a number of advantages, such as providing precise interrupts and avoiding complications with the memory consistency model, it requires the core to hold on to resources (reorder buffer entries, load/store queue entries, physical registers) until they are released in program order. In contrast, out-of-order commit can release some resources much earlier, yielding improved performance and/or lower resource requirements. Non-speculative out-of-order commit is limited in terms of correctness by the conditions described in the work of Bell and Lipasti (2004). In this paper we revisit out-of-order commit by examining the potential performance benefits of lifting these conditions one by one and in combination, for both non-speculative and speculative out-of-order commit. While correctly handling recovery for all out-of-order commit conditions currently requires complex tracking and expensive checkpointing, this work aims to demonstrate the potential for selective, speculative out-of-order commit using an oracle implementation without speculative rollback costs. Through this analysis of the potential of out-of-order commit, we learn that: a) there is significant untapped potential for aggressive variants of out-of-order commit; b) it is important to optimize the out-of-order commit depth for a balanced design, as smaller cores benefit from reduced depth while larger cores continue to benefit from deeper designs; c) the focus on implementing only a subset of the out-of-order commit conditions could lead to efficient implementations; d) the benefits of out-of-order commit increases with higher memory latency and in conjunction with prefetching; e) out-of-order commit exposes additional parallelism in the memory hierarchy.

  • 4.
    Alipour, Mehdi
    et al.
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    Carlson, Trevor E.
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    Kaxiras, Stefanos
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    Exploring the performance limits of out-of-order commit2017Ingår i: Proc. 14th Computing Frontiers Conference, New York: ACM Press, 2017, s. 211-220Konferensbidrag (Refereegranskat)
  • 5.
    Alipour, Mehdi
    et al.
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorteknik. Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    Kumar, Rakesh
    Norwegian Univ Sci & Technol, Dept Comp Sci, Trondheim, Norway.
    Kaxiras, Stefanos
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorteknik.
    Black-Schaffer, David
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorteknik.
    FIFOrder MicroArchitecture: Ready-Aware Instruction Scheduling for OoO Processors2019Ingår i: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), IEEE, 2019, s. 716-721Konferensbidrag (Refereegranskat)
    Abstract [en]

    The number of instructions a processor's instruction queue can examine (depth) and the number it can issue together (width) determine its ability to take advantage of the ILP in an application. Unfortunately, increasing either the width or depth of the instruction queue is very costly due to the content-addressable logic needed to wakeup and select instructions out-of-order. This work makes the observation that a large number of instructions have both operands ready at dispatch, and therefore do not benefit from out-of-order scheduling. We leverage this to place such ready-at-dispatch instructions in separate, simpler, in-order FIFO queues for scheduling. With such additional queues, we can reduce the size and width of the expensive out-of-order instruction queue, without reducing the processor's overall issue width and depth. Our design, FIFOrder, is able to steer more than 60% of instructions to the cheaper FIFO queues, providing a 50% energy savings over a traditional out-of-order instruction queue design, while delivering 8% higher performance.

  • 6.
    Alirezaie, Marjan
    et al.
    Örebro University.
    Renoux, Jennifer
    Örebro University.
    Köckemann, Uwe
    Örebro University.
    Kristoffersson, Annica
    Örebro University.
    Karlsson, Lars
    Örebro University.
    Blomqvist, Eva
    SICS East.
    Tsiftes, Nicolas
    SICS.
    Voigt, Thiemo
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation. SICS.
    Loutfi, Amy
    Örebro University.
    An Ontology-based Context-aware System for Smart Homes: E-care@ home2017Ingår i: Sensors, ISSN 1424-8220, E-ISSN 1424-8220, Vol. 17, nr 7Artikel i tidskrift (Refereegranskat)
  • 7. Alonso, Juan M.
    et al.
    Nordhamn, Amanda
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    Olofsson, Simon
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    Voigt, Thiemo
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    Bounds on the lifetime of wireless sensor networks with lossy links and directional antennas2016Ingår i: Wireless Network Performance Enhancement via Directional Antennas: Models, Protocols, and Systems, Boca Raton, FL: CRC Press, 2016, s. 329-361Kapitel i bok, del av antologi (Refereegranskat)
  • 8.
    Alves, Ricardo
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Avdelningen för datorteknik. Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    Leveraging Existing Microarchitectural Structures to Improve First-Level Caching Efficiency2019Doktorsavhandling, sammanläggning (Övrigt vetenskapligt)
    Abstract [en]

    Low-latency data access is essential for performance. To achieve this, processors use fast first-level caches combined with out-of-order execution, to decrease and hide memory access latency respectively. While these approaches are effective for performance, they cost significant energy, leading to the development of many techniques that require designers to trade-off performance and efficiency.

    Way-prediction and filter caches are two of the most common strategies for improving first-level cache energy efficiency while still minimizing latency. They both have compromises as way-prediction trades off some latency for better energy efficiency, while filter caches trade off some energy efficiency for lower latency. However, these strategies are not mutually exclusive. By borrowing elements from both, and taking into account SRAM memory layout limitations, we proposed a novel MRU-L0 cache that mitigates many of their shortcomings while preserving their benefits. Moreover, while first-level caches are tightly integrated into the cpu pipeline, existing work on these techniques largely ignores the impact they have on instruction scheduling. We show that the variable hit latency introduced by way-misspredictions causes instruction replays of load dependent instruction chains, which hurts performance and efficiency. We study this effect and propose a variable latency cache-hit instruction scheduler, that identifies potential misschedulings, reduces instruction replays, reduces negative performance impact, and further improves cache energy efficiency.

    Modern pipelines also employ sophisticated execution strategies to hide memory latency and improve performance. While their primary use is for performance and correctness, they require intermediate storage that can be used as a cache as well. In this work we demonstrate how the store-buffer, paired with the memory dependency predictor, can be used to efficiently cache dirty data; and how the physical register file, paired with a value predictor, can be used to efficiently cache clean data. These strategies not only improve both performance and energy, but do so with no additional storage and minimal additional complexity, since they recycle existing cpu structures to detect reuse, memory ordering violations, and misspeculations.

    Delarbeten
    1. Addressing energy challenges in filter caches
    Öppna denna publikation i ny flik eller fönster >>Addressing energy challenges in filter caches
    2017 (Engelska)Ingår i: Proc. 29th International Symposium on Computer Architecture and High Performance Computing, IEEE Computer Society, 2017, s. 49-56Konferensbidrag, Publicerat paper (Refereegranskat)
    Abstract [en]

    Filter caches and way-predictors are common approaches to improve the efficiency and/or performance of first-level caches. Filter caches use a small L0 to provide more efficient and faster access to a small subset of the data, and work well for programs with high locality. Way-predictors improve efficiency by accessing only the way predicted, which alleviates the need to read all ways in parallel without increasing latency, but hurts performance due to mispredictions.In this work we examine how SRAM layout constraints (h-trees and data mapping inside the cache) affect way-predictors and filter caches. We show that accessing the smaller L0 array can be significantly more energy efficient than attempting to read fewer ways from a larger L1 cache; and that the main source of energy inefficiency in filter caches comes from L0 and L1 misses. We propose a filter cache optimization that shares the tag array between the L0 and the L1, which incurs the overhead of reading the larger tag array on every access, but in return allows us to directly access the correct L1 way on each L0 miss. This optimization does not add any extra latency and counter-intuitively, improves the filter caches overall energy efficiency beyond that of the way-predictor.By combining the low power benefits of a physically smaller L0 with the reduction in miss energy by reading L1 tags upfront in parallel with L0 data, we show that the optimized filter cache reduces the dynamic cache energy compared to a traditional filter cache by 26% while providing the same performance advantage. Compared to a way-predictor, the optimized cache improves performance by 6% and energy by 2%.

    Ort, förlag, år, upplaga, sidor
    IEEE Computer Society, 2017
    Nationell ämneskategori
    Datavetenskap (datalogi)
    Identifikatorer
    urn:nbn:se:uu:diva-334221 (URN)10.1109/SBAC-PAD.2017.14 (DOI)000426895600007 ()978-1-5090-1233-6 (ISBN)
    Konferens
    29th International Symposium on Computer Architecture and High Performance Computing SBAC-PAD, 2017, October 17–20, Campinas, Brazil.
    Tillgänglig från: 2017-11-09 Skapad: 2017-11-21 Senast uppdaterad: 2019-05-22Bibliografiskt granskad
    2. Dynamically Disabling Way-prediction to Reduce Instruction Replay
    Öppna denna publikation i ny flik eller fönster >>Dynamically Disabling Way-prediction to Reduce Instruction Replay
    2018 (Engelska)Ingår i: 2018 IEEE 36th International Conference on Computer Design (ICCD), IEEE, 2018, s. 140-143Konferensbidrag, Publicerat paper (Refereegranskat)
    Abstract [en]

    Way-predictors have long been used to reduce dynamic cache energy without the performance loss of serial caches. However, they produce variable-latency hits, as incorrect predictions increase load-to-use latency. While the performance impact of these extra cycles has been well-studied, the need to replay subsequent instructions in the pipeline due to the load latency increase has been ignored. In this work we show that way-predictors pay a significant performance penalty beyond previously studied effects due to instruction replays caused by mispredictions. To address this, we propose a solution that learns the confidence of the way prediction and dynamically disables it when it is likely to mispredict and cause replays. This allows us to reduce cache latency (when we can trust the way-prediction) while still avoiding the need to replay instructions in the pipeline (by avoiding way-mispredictions). Standard way-predictors degrade IPC by 6.9% vs. a parallel cache due to 10% of the instructions being replayed (worst case 42.3%). While our solution decreases way-prediction accuracy by turning off the way-predictor in some cases when it would have been correct, it delivers higher performance than a standard way-predictor. Our confidence-based way-predictor degrades IPC by only 4.4% by replaying just 5.6% of the instructions (worse case 16.3%). This reduces the way-predictor cache energy overhead compared to serial access cache, from 8.5% to 3.7% on average and on the worst case, from 33.8% to 9.5%.

    Ort, förlag, år, upplaga, sidor
    IEEE, 2018
    Serie
    Proceedings IEEE International Conference on Computer Design, ISSN 1063-6404, E-ISSN 2576-6996
    Nationell ämneskategori
    Datavetenskap (datalogi)
    Identifikatorer
    urn:nbn:se:uu:diva-361215 (URN)10.1109/ICCD.2018.00029 (DOI)000458293200018 ()978-1-5386-8477-1 (ISBN)
    Konferens
    IEEE 36th International Conference on Computer Design (ICCD), October 7–10, 2018, Orlando, FL, USA
    Tillgänglig från: 2018-09-21 Skapad: 2018-09-21 Senast uppdaterad: 2019-05-22Bibliografiskt granskad
    3. Minimizing Replay under Way-Prediction
    Öppna denna publikation i ny flik eller fönster >>Minimizing Replay under Way-Prediction
    2019 (Engelska)Rapport (Övrigt vetenskapligt)
    Abstract [en]

    Way-predictors are effective at reducing dynamic cache energy by reducing the number of ways accessed, but introduce additional latency for incorrect way-predictions. While previous work has studied the impact of the increased latency for incorrect way-predictions, we show that the latency variability has a far greater effect as it forces replay of in-flight instructions on an incorrect way-prediction. To address the problem, we propose a solution that learns the confidence of the way-prediction and dynamically disables it when it is likely to mispredict. We further improve this approach by biasing the confidence to reduce latency variability further at the cost of reduced way-predictions. Our results show that instruction replay in a way-predictor reduces IPC by 6.9% due to 10% of the instructions being replayed. Our confidence-based way-predictor degrades IPC by only 2.9% by replaying just 3.4% of the instructions, reducing way-predictor cache energy overhead (compared to serial access cache) from 8.5% to 1.9%.

    Serie
    Technical report / Department of Information Technology, Uppsala University, ISSN 1404-3203 ; 2019-003
    Nationell ämneskategori
    Datavetenskap (datalogi)
    Identifikatorer
    urn:nbn:se:uu:diva-383596 (URN)
    Tillgänglig från: 2019-05-17 Skapad: 2019-05-17 Senast uppdaterad: 2019-07-03Bibliografiskt granskad
    4. Filter caching for free: The untapped potential of the store-buffer
    Öppna denna publikation i ny flik eller fönster >>Filter caching for free: The untapped potential of the store-buffer
    2019 (Engelska)Ingår i: Proc. 46th International Symposium on Computer Architecture, New York: ACM Press, 2019, s. 436-448Konferensbidrag, Publicerat paper (Refereegranskat)
    Abstract [en]

    Modern processors contain store-buffers to allow stores to retire under a miss, thus hiding store-miss latency. The store-buffer needs to be large (for performance) and searched on every load (for correctness), thereby making it a costly structure in both area and energy. Yet on every load, the store-buffer is probed in parallel with the L1 and TLB, with no concern for the store-buffer's intrinsic hit rate or whether a store-buffer hit can be predicted to save energy by disabling the L1 and TLB probes.

    In this work we cache data that have been written back to memory in a unified store-queue/buffer/cache, and predict hits to avoid L1/TLB probes and save energy. By dynamically adjusting the allocation of entries between the store-queue/buffer/cache, we can achieve nearly optimal reuse, without causing stalls. We are able to do this efficiently and cheaply by recognizing key properties of stores: free caching (since they must be written into the store-buffer for correctness we need no additional data movement), cheap coherence (since we only need to track state changes of the local, dirty data in the store-buffer), and free and accurate hit prediction (since the memory dependence predictor already does this for scheduling).

    As a result, we are able to increase the store-buffer hit rate and reduce store-buffer/TLB/L1 dynamic energy by 11.8% (up to 26.4%) on SPEC2006 without hurting performance (average IPC improvements of 1.5%, up to 4.7%).The cost for these improvements is a 0.2% increase in L1 cache capacity (1 bit per line) and one additional tail pointer in the store-buffer.

    Ort, förlag, år, upplaga, sidor
    New York: ACM Press, 2019
    Nationell ämneskategori
    Datavetenskap (datalogi)
    Identifikatorer
    urn:nbn:se:uu:diva-383473 (URN)10.1145/3307650.3322269 (DOI)978-1-4503-6669-4 (ISBN)
    Konferens
    ISCA 2019, June 22–26, Phoenix, AZ
    Forskningsfinansiär
    Knut och Alice Wallenbergs StiftelseEU, Horisont 2020, 715283EU, Horisont 2020, 801051Stiftelsen för strategisk forskning (SSF), SM17-0064
    Tillgänglig från: 2019-06-22 Skapad: 2019-05-16 Senast uppdaterad: 2019-07-03Bibliografiskt granskad
    5.
    Posten kunde inte hittas. Det kan bero på att posten inte längre är tillgänglig eller att du har råkat ange ett felaktigt id i adressfältet.
  • 9.
    Alves, Ricardo
    et al.
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    Kaxiras, Stefanos
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    Black-Schaffer, David
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    Dynamically Disabling Way-prediction to Reduce Instruction Replay2018Ingår i: 2018 IEEE 36th International Conference on Computer Design (ICCD), IEEE, 2018, s. 140-143Konferensbidrag (Refereegranskat)
    Abstract [en]

    Way-predictors have long been used to reduce dynamic cache energy without the performance loss of serial caches. However, they produce variable-latency hits, as incorrect predictions increase load-to-use latency. While the performance impact of these extra cycles has been well-studied, the need to replay subsequent instructions in the pipeline due to the load latency increase has been ignored. In this work we show that way-predictors pay a significant performance penalty beyond previously studied effects due to instruction replays caused by mispredictions. To address this, we propose a solution that learns the confidence of the way prediction and dynamically disables it when it is likely to mispredict and cause replays. This allows us to reduce cache latency (when we can trust the way-prediction) while still avoiding the need to replay instructions in the pipeline (by avoiding way-mispredictions). Standard way-predictors degrade IPC by 6.9% vs. a parallel cache due to 10% of the instructions being replayed (worst case 42.3%). While our solution decreases way-prediction accuracy by turning off the way-predictor in some cases when it would have been correct, it delivers higher performance than a standard way-predictor. Our confidence-based way-predictor degrades IPC by only 4.4% by replaying just 5.6% of the instructions (worse case 16.3%). This reduces the way-predictor cache energy overhead compared to serial access cache, from 8.5% to 3.7% on average and on the worst case, from 33.8% to 9.5%.

  • 10.
    Alves, Ricardo
    et al.
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    Kaxiras, Stefanos
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    Black-Schaffer, David
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    Minimizing Replay under Way-Prediction2019Rapport (Övrigt vetenskapligt)
    Abstract [en]

    Way-predictors are effective at reducing dynamic cache energy by reducing the number of ways accessed, but introduce additional latency for incorrect way-predictions. While previous work has studied the impact of the increased latency for incorrect way-predictions, we show that the latency variability has a far greater effect as it forces replay of in-flight instructions on an incorrect way-prediction. To address the problem, we propose a solution that learns the confidence of the way-prediction and dynamically disables it when it is likely to mispredict. We further improve this approach by biasing the confidence to reduce latency variability further at the cost of reduced way-predictions. Our results show that instruction replay in a way-predictor reduces IPC by 6.9% due to 10% of the instructions being replayed. Our confidence-based way-predictor degrades IPC by only 2.9% by replaying just 3.4% of the instructions, reducing way-predictor cache energy overhead (compared to serial access cache) from 8.5% to 1.9%.

  • 11.
    Alves, Ricardo
    et al.
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    Nikoleris, Nikos
    ARM Res, Lund, Sweden.
    Kaxiras, Stefanos
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    Black-Schaffer, David
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    Addressing energy challenges in filter caches2017Ingår i: Proc. 29th International Symposium on Computer Architecture and High Performance Computing, IEEE Computer Society, 2017, s. 49-56Konferensbidrag (Refereegranskat)
    Abstract [en]

    Filter caches and way-predictors are common approaches to improve the efficiency and/or performance of first-level caches. Filter caches use a small L0 to provide more efficient and faster access to a small subset of the data, and work well for programs with high locality. Way-predictors improve efficiency by accessing only the way predicted, which alleviates the need to read all ways in parallel without increasing latency, but hurts performance due to mispredictions.In this work we examine how SRAM layout constraints (h-trees and data mapping inside the cache) affect way-predictors and filter caches. We show that accessing the smaller L0 array can be significantly more energy efficient than attempting to read fewer ways from a larger L1 cache; and that the main source of energy inefficiency in filter caches comes from L0 and L1 misses. We propose a filter cache optimization that shares the tag array between the L0 and the L1, which incurs the overhead of reading the larger tag array on every access, but in return allows us to directly access the correct L1 way on each L0 miss. This optimization does not add any extra latency and counter-intuitively, improves the filter caches overall energy efficiency beyond that of the way-predictor.By combining the low power benefits of a physically smaller L0 with the reduction in miss energy by reading L1 tags upfront in parallel with L0 data, we show that the optimized filter cache reduces the dynamic cache energy compared to a traditional filter cache by 26% while providing the same performance advantage. Compared to a way-predictor, the optimized cache improves performance by 6% and energy by 2%.

  • 12.
    Alves, Ricardo
    et al.
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    Ros, Alberto
    Black-Schaffer, David
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    Kaxiras, Stefanos
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    Filter caching for free: The untapped potential of the store-buffer2019Ingår i: Proc. 46th International Symposium on Computer Architecture, New York: ACM Press, 2019, s. 436-448Konferensbidrag (Refereegranskat)
    Abstract [en]

    Modern processors contain store-buffers to allow stores to retire under a miss, thus hiding store-miss latency. The store-buffer needs to be large (for performance) and searched on every load (for correctness), thereby making it a costly structure in both area and energy. Yet on every load, the store-buffer is probed in parallel with the L1 and TLB, with no concern for the store-buffer's intrinsic hit rate or whether a store-buffer hit can be predicted to save energy by disabling the L1 and TLB probes.

    In this work we cache data that have been written back to memory in a unified store-queue/buffer/cache, and predict hits to avoid L1/TLB probes and save energy. By dynamically adjusting the allocation of entries between the store-queue/buffer/cache, we can achieve nearly optimal reuse, without causing stalls. We are able to do this efficiently and cheaply by recognizing key properties of stores: free caching (since they must be written into the store-buffer for correctness we need no additional data movement), cheap coherence (since we only need to track state changes of the local, dirty data in the store-buffer), and free and accurate hit prediction (since the memory dependence predictor already does this for scheduling).

    As a result, we are able to increase the store-buffer hit rate and reduce store-buffer/TLB/L1 dynamic energy by 11.8% (up to 26.4%) on SPEC2006 without hurting performance (average IPC improvements of 1.5%, up to 4.7%).The cost for these improvements is a 0.2% increase in L1 cache capacity (1 bit per line) and one additional tail pointer in the store-buffer.

  • 13.
    Aris, Ahmet
    et al.
    Istanbul Technical University.
    Oktuğ, Sema
    Istanbul Technical University.
    Voigt, Thiemo
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    Security of Internet of Things for a Reliable Internet of Services2018Ingår i: Autonomous Control for a Reliable Internet of Services: Methods, Models, Approaches, Techniques, Algorithms, and Tools / [ed] Ivan Ganchev, R. D. van der Mei, Hans van den Berg, Cham , 2018Kapitel i bok, del av antologi (Refereegranskat)
  • 14.
    Asan, Noor Badariah
    et al.
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Tekniska sektionen, Institutionen för teknikvetenskaper, Fasta tillståndets elektronik. Universiti Teknikal Malaysia Melaka, Melaka Malaysia.
    Carlos, Pérez Penichet
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    Redzwan, Syaiful
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Tekniska sektionen, Institutionen för teknikvetenskaper, Fasta tillståndets elektronik.
    Noreland, Daniel
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi.
    Hassan, Emadeldeen
    Umeå University.
    Rydberg, Anders
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Tekniska sektionen, Institutionen för teknikvetenskaper, Fasta tillståndets elektronik.
    Blokhuis, Taco
    Maastricht University Medical Center+, Netherlands.
    Voigt, Thiemo
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    Augustine, Robin
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Tekniska sektionen, Institutionen för teknikvetenskaper, Fasta tillståndets elektronik.
    Data Packet Transmission through Fat Tissue for Wireless Intra-Body Networks2017Ingår i: IEEE Journal of Electromagnetics, RF and Microwaves in Medicine and Biology, ISSN 2469-7249, Vol. 1, nr 2, s. 43-51Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    This work explores high data rate microwave communication through fat tissue in order to address the wide bandwidth requirements of intra-body area networks. We have designed and carried out experiments on an IEEE 802.15.4 based WBAN prototype by measuring the performance of the fat tissue channel in terms of data packet reception with respect to tissue length and power transmission. This paper proposes and demonstrates a high data rate communication channel through fat tissue using phantom and ex-vivo environments. Here, we achieve a data packet reception of approximately 96 % in both environments. The results also show that the received signal strength drops by ~1 dBm per 10 mm in phantom and ~2 dBm per 10 mm in ex-vivo. The phantom and ex-vivo experimentations validated our approach for high data rate communication through fat tissue for intrabody network applications. The proposed method opens up new opportunities for further research in fat channel communication. This study will contribute to the successful development of high bandwidth wireless intra-body networks that support high data rate implanted, ingested, injected, or worn devices

  • 15.
    Asan, Noor Badariah
    et al.
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Tekniska sektionen, Institutionen för teknikvetenskaper, Fasta tillståndets elektronik. Faculty of Electronic and Computer Engineering, Universiti Teknikal Malaysia Melaka.
    Hassan, Emadeldeen
    Perez, Mauricio D.
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Tekniska sektionen, Institutionen för teknikvetenskaper, Fasta tillståndets elektronik.
    Joseph, Laya
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Tekniska sektionen, Institutionen för teknikvetenskaper, Fasta tillståndets elektronik.
    Berggren, Martin
    Voigt, Thiemo
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    Augustine, Robin
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Tekniska sektionen, Institutionen för teknikvetenskaper, Fasta tillståndets elektronik.
    Fat-intrabody communication at 5.8 GHz including impacts of dynamics body movementsManuskript (preprint) (Övrigt vetenskapligt)
  • 16.
    Asan, Noor Badariah
    et al.
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Tekniska sektionen, Institutionen för teknikvetenskaper, Fasta tillståndets elektronik. Univ Tekn Malaysia Melaka, Fac Elect & Comp Engn, Durian Tunggal 76100, Malaysia.
    Hassan, Emadeldeen
    Umea Univ, Dept Comp Sci, S-90187 Umea, Sweden;Menoufia Univ, Dept Elect & Elect Commun, Menoufia 32952, Egypt.
    Perez, Mauricio David
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Tekniska sektionen, Institutionen för teknikvetenskaper, Fasta tillståndets elektronik.
    Shah, Syaiful Redzwan Mohd
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Tekniska sektionen, Institutionen för teknikvetenskaper, Fasta tillståndets elektronik.
    Velander, Jacob
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Tekniska sektionen, Institutionen för teknikvetenskaper, Fasta tillståndets elektronik.
    Blokhuis, Taco J.
    Maastricht Univ, Dept Surg, Med Ctr, NL-6229 HX Maastricht, Netherlands.
    Voigt, Thiemo
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation. ¨.
    Augustine, Robin
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Tekniska sektionen, Institutionen för teknikvetenskaper, Fasta tillståndets elektronik.
    Assessment of Blood Vessel Effect on Fat-Intrabody Communication Using Numerical and Ex-Vivo Models at 2.45 GHZ2019Ingår i: IEEE Access, E-ISSN 2169-3536, Vol. 7, s. 89886-89900Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    The potential offered by the intra-body communication (IBC) over the past few years has resulted in a spike of interest for the topic, specifically for medical applications. Fat-IBC is subsequently a novel alternative technique that utilizes fat tissue as a communication channel. This work aimed to identify such transmission medium and its performance in varying blood-vessel systems at 2.45 GHz, particularly in the context of the IBC and medical applications. It incorporated three-dimensional (3D) electromagnetic simulations and laboratory investigations that implemented models of blood vessels of varying orientations, sizes, and positions. Such investigations were undertaken by using ex-vivo porcine tissues and three blood-vessel system configurations. These configurations represent extreme cases of real-life scenarios that sufficiently elucidated their principal influence on the transmission. The blood-vessel models consisted of ex-vivo muscle tissues and copper rods. The results showed that the blood vessels crossing the channel vertically contributed to 5.1 dB and 17.1 dB signal losses for muscle and copper rods, respectively, which is the worst-case scenario in the context of fat-channel with perturbance. In contrast, blood vessels aligned-longitudinally in the channel have less effect and yielded 4.5 dB and 4.2 dB signal losses for muscle and copper rods, respectively. Meanwhile, the blood vessels crossing the channel horizontally displayed 3.4 dB and 1.9 dB signal losses for muscle and copper rods, respectively, which were the smallest losses among the configurations. The laboratory investigations were in agreement with the simulations. Thus, this work substantiated the fat-IBC signal transmission variability in the context of varying blood vessel configurations.

  • 17.
    Asan, Noor Badariah
    et al.
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Tekniska sektionen, Institutionen för teknikvetenskaper, Fasta tillståndets elektronik.
    Hassan, Emadeldeen
    Umea Univ, Dept Comp Sci, S-90187 Umea, Sweden;Menoufia Univ, Dept Elect & Elect Commun, Menoufia 32952, Egypt.
    Velander, Jacob
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Tekniska sektionen, Institutionen för teknikvetenskaper, Fasta tillståndets elektronik.
    Redzwan, Syaiful
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Tekniska sektionen, Institutionen för teknikvetenskaper, Fasta tillståndets elektronik.
    Noreland, Daniel
    Umea Univ, Dept Comp Sci, S-90187 Umea, Sweden.
    Blokhuis, Taco J.
    Maastricht Univ, Med Ctr, Dept Surg, NL-6229 HX Maastricht, Netherlands.
    Wadbro, Eddie
    Umea Univ, Dept Comp Sci, S-90187 Umea, Sweden.
    Berggren, Martin
    Umea Univ, Dept Comp Sci, S-90187 Umea, Sweden.
    Voigt, Thiemo
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    Augustine, Robin
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Tekniska sektionen, Institutionen för teknikvetenskaper, Fasta tillståndets elektronik.
    Characterization of the Fat Channel for Intra-Body Communication at R-Band Frequencies2018Ingår i: Sensors, ISSN 1424-8220, E-ISSN 1424-8220, Vol. 18, nr 9, artikel-id 2752Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    In this paper, we investigate the use of fat tissue as a communication channel between in-body, implanted devices at R-band frequencies (1.7-2.6 GHz). The proposed fat channel is based on an anatomical model of the human body. We propose a novel probe that is optimized to efficiently radiate the R-band frequencies into the fat tissue. We use our probe to evaluate the path loss of the fat channel by studying the channel transmission coefficient over the R-band frequencies. We conduct extensive simulation studies and validate our results by experimentation on phantom and ex-vivo porcine tissue, with good agreement between simulations and experiments. We demonstrate a performance comparison between the fat channel and similar waveguide structures. Our characterization of the fat channel reveals propagation path loss of similar to 0.7 dB and similar to 1.9 dB per cm for phantom and ex-vivo porcine tissue, respectively. These results demonstrate that fat tissue can be used as a communication channel for high data rate intra-body networks.

  • 18.
    Asan, Noor Badariah
    et al.
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Tekniska sektionen, Institutionen för teknikvetenskaper, Fasta tillståndets elektronik.
    Noreland, Daniel
    Department of Computing Science, Umeå University, SE-901 87 Umeå, Sweden.
    Hassan, Emadeldeen
    Department of Computing Science, Umeå University, SE-901 87 Umeå, Sweden; Department of Electronics and Electrical Communications, Menoufia University, 32952 Menouf, Egypt.
    Redzwan, Syaiful
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Tekniska sektionen, Institutionen för teknikvetenskaper, Fasta tillståndets elektronik.
    Rydberg, Anders
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Tekniska sektionen, Institutionen för teknikvetenskaper, Fasta tillståndets elektronik.
    Blokhuis, Taco J.
    Department of Surgery, Maastricht University Medical Center+, P. Debyelaan 25, 6229 HX Maastricht, The Netherlands.
    Carlsson, Per-Ola
    Uppsala universitet, Medicinska och farmaceutiska vetenskapsområdet, Medicinska fakulteten, Institutionen för medicinska vetenskaper, Transplantation och regenerativ medicin.
    Voigt, Thiemo
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    Augustine, Robin
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Tekniska sektionen, Institutionen för teknikvetenskaper, Fasta tillståndets elektronik.
    Intra-body microwave communication through adipose tissue2017Ingår i: Healthcare Technology Letters, E-ISSN 2053-3713, Vol. 4, nr 4, s. 115-121Artikel i tidskrift (Refereegranskat)
  • 19.
    Asan, Noor Badariah
    et al.
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Tekniska sektionen, Institutionen för teknikvetenskaper, Fasta tillståndets elektronik.
    Redzwan, Syaiful
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Tekniska sektionen, Institutionen för teknikvetenskaper, Fasta tillståndets elektronik.
    Rydberg, Anders
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Tekniska sektionen, Institutionen för teknikvetenskaper, Fasta tillståndets elektronik.
    Augustine, Robin
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Tekniska sektionen, Institutionen för teknikvetenskaper, Fasta tillståndets elektronik.
    Noreland, Daniel
    Hassan, Emadeldeen
    Voigt, Thiemo
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    Human fat tissue: A microwave communication channel2017Ingår i: Proc. 1st MTT-S International Microwave Bio Conference, IEEE, 2017Konferensbidrag (Refereegranskat)
    Abstract [en]

    In this paper, we present an approach for communication through human body tissue in the R-band frequency range. This study examines the ranges of microwave frequencies suitable for intra-body communication. The human body tissues are characterized with respect to their transmission properties using simulation modeling and phantom measurements. The variations in signal coupling with respect to different tissue thicknesses are studied. The simulation and phantom measurement results show that electromagnetic communication in the fat layer is viable with attenuation of approximately 2 dB per 20 mm. 

  • 20.
    Asan, Noor Badariah
    et al.
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Tekniska sektionen, Institutionen för teknikvetenskaper, Fasta tillståndets elektronik.
    Velander, Jacob
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Tekniska sektionen, Institutionen för teknikvetenskaper, Fasta tillståndets elektronik.
    Redzwan, Syaiful
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Tekniska sektionen, Institutionen för teknikvetenskaper, Fasta tillståndets elektronik.
    Augustine, Robin
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Tekniska sektionen, Institutionen för teknikvetenskaper, Fasta tillståndets elektronik.
    Hassan, Emadeldeen
    Department of Computing Science, Umeå University, Umeå, Sweden.
    Noreland, Daniel
    Department of Computing Science, Umeå University, Umeå, Sweden.
    Voigt, Thiemo
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    Blokhuis, Taco J.
    Department of Surgery, Maastricht University Medical Center+, Maastricht, The Netherland.
    Reliability of the fat tissue channel for intra-body microwave communication2017Ingår i: 2017 IEEE Conference on Antenna Measurements & Applications (CAMA), IEEE, 2017, s. 310-313Konferensbidrag (Refereegranskat)
    Abstract [en]

    Recently, the human fat tissue has been proposed as a microwave channel for intra-body sensor applications. In this work, we assess how disturbances can prevent reliable microwave propagation through the fat channel. Perturbants of different sizes are considered. The simulation and experimental results show that efficient communication through the fat channel is possible even in the presence of perturbants such as embedded muscle layers and blood vessels. We show that the communication channel is not affected by perturbants that are smaller than 15 mm cube.

  • 21.
    Asan, Noor Badariah
    et al.
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Tekniska sektionen, Institutionen för teknikvetenskaper, Fasta tillståndets elektronik.
    Velander, Jacob
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Tekniska sektionen, Institutionen för teknikvetenskaper, Fasta tillståndets elektronik.
    Redzwan, Syaiful
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Tekniska sektionen, Institutionen för teknikvetenskaper, Fasta tillståndets elektronik.
    Perez, Mauricio D.
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Tekniska sektionen, Institutionen för teknikvetenskaper, Fasta tillståndets elektronik.
    Hassan, Emadeldeen
    Umeå University, Department of Computing Science, Umeå, Sweden.
    Blokhuis, Taco J.
    Maastricht University Medical Center, Department of Surgery, Maastricht, The Netherland.
    Voigt, Thiemo
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    Augustine, Robin
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Tekniska sektionen, Institutionen för teknikvetenskaper, Fasta tillståndets elektronik.
    Effect of thickness inhomogeneity in fat tissue on in-body microwave propagation2018Ingår i: 2018 IEEE International Microwave Biomedical Conference (IMBioC), Philadelphia, USA: IEEE, 2018, s. 136-138Konferensbidrag (Refereegranskat)
    Abstract [en]

    In recent studies, it has been found that fat tissue can be used as a microwave communication channel. In this article, the effect of thickness inhomogeneities in fat tissues on the performance of in-body microwave communication at 2.45 GHz is investigated using phantom models. We considered two models namely concave and convex geometrical fat distribution to account for the thickness inhomogeneities. The thickness of the fat tissue is varied from 5 mm to 45 mm and the Gap between the transmitter/receiver and the starting and ending of concavity/convexity is varied from 0 mm to 25 mm for a length of 100 mm to study the behavior in the microwave propagation. The phantoms of different geometries, concave and convex, are used in this work to validate the numerical studies. It was noticed that the convex model exhibited higher signal coupling by an amount of 1 dB (simulation) and 2 dB (measurement) compared to the concave model. From the study, it was observed that the signal transmission improves up to 30 mm thick fat and reaches a plateau when the thickness is increased further.

  • 22.
    Bagci, Ibrahim Ethem
    et al.
    Univ Lancaster, Sch Comp & Commun, Lancaster, England.
    Raza, Shahid
    SICS Swedish ICT, Kista, Sweden.
    Roedig, Utz
    Univ Lancaster, Sch Comp & Commun, Lancaster, England.
    Voigt, Thiemo
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation. SICS Swedish ICT, Kista, Sweden.
    Fusion: Coalesced Confidential Storage and Communication Framework for the IoT2016Ingår i: Security and Communication Networks, ISSN 1939-0114, E-ISSN 1939-0122, Vol. 9, nr 15, s. 2656-2673Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    Comprehensive security mechanisms are required for a successful implementation of the Internet of Things (IoT). Existing solutions focus mainly on securing the communication links between Internet hosts and IoT devices. However, as most IoT devices nowadays provide vast amounts of flash storage space, it is as well required to consider storage security within a comprehensive security framework. Instead of developing independent security solutions for storage and communication, we propose Fusion, a framework that provides coalesced confidential storage and communication. Fusion uses existing secure communication protocols for the IoT such as Internet protocol security (IPsec) and datagram transport layer security (DTLS) and re-uses the defined communication security mechanisms within the storage component. Thus, trusted mechanisms developed for communication security are extended into the storage space. Notably, this mechanism allows us to transmit requested data directly from the file system without decrypting read data blocks and then re-encrypting these for transmission. Thus, Fusion provides benefits in terms of processing speed and energy efficiency, which are important aspects for resource-constrained IoT devices. This paper describes the Fusion architecture and its instantiation for IPsec-based and DTLS-based systems. We describe Fusion's implementation and evaluate its storage overheads, communication performance, and energy consumption.

  • 23. Baird, Ryan
    et al.
    Gavin, Peter
    Själander, Magnus
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    Whalley, David
    Uh, Gang-Ryung
    Optimizing transfers of control in the static pipeline architecture2015Ingår i: Proc. 16th ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems, New York: ACM Press, 2015, s. 7-16Konferensbidrag (Refereegranskat)
    Abstract [en]

    Statically pipelined processors offer a new way to improve the performance beyond that of a traditional in-order pipeline while simultaneously reducing energy usage by enabling the compiler to control more fine-grained details of the program execution. This paper describes how a compiler can exploit the features of the static pipeline architecture to apply optimizations on transfers of control that are not possible on a conventional architecture. The optimizations presented in this paper include hoisting the target address calculations for branches, jumps, and calls out of loops, performing branch chaining between calls and jumps, hoisting the setting of return addresses out of loops, and exploiting conditional calls and returns. The benefits of performing these transfer of control optimizations include a 6.8% reduction in execution time and a 3.6% decrease in estimated energy usage.

  • 24. Bardizbanyan, Alen
    et al.
    Själander, Magnus
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    Whalley, David
    Larsson-Edefors, Per
    Improving data access efficiency by using context-aware loads and stores2015Ingår i: Proc. 16th ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems, New York: ACM Press, 2015, s. 27-36Konferensbidrag (Refereegranskat)
    Abstract [en]

    Memory operations have a significant impact on both performance and energy usage even when an access hits in the level-one data cache (L1 DC). Load instructions in particular affect performance as they frequently result in stalls since the register to be loaded is often referenced before the data is available in the pipeline. L1 DC accesses also impact energy usage as they typically require significantly more energy than a register file access. Despite their impact on performance and energy usage, L1 DC accesses on most processors are performed in a general fashion without regard to the context in which the load or store operation is performed. We describe a set of techniques where the compiler enhances load and store instructions so that they can be executed with fewer stalls and/or enable the L1 DC to be accessed in a more energy-efficient manner. We show that using these techniques can simultaneously achieve a 6% gain in performance and a 43% reduction in L1 DC energy usage.

  • 25.
    Bor, Martin
    et al.
    Lancaster University.
    Roedig, Utz
    Lancaster University.
    Voigt, Thiemo
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    Alonso, Juan
    Univ. Nac. de Cuyo, Argentina.
    Do LoRa Low-Power Wide-Area Networks Scale?2016Konferensbidrag (Refereegranskat)
    Abstract [en]

    New Internet of Things (IoT) technologies such as LongRange (LoRa) are emerging which enable power ecientwireless communication over very long distances. Devicestypically communicate directly to a sink node which removesthe need of constructing and maintaining a complex multi-hop network. Given the fact that a wide area is coveredand that all devices communicate directly to a few sinknodes a large number of nodes have to share the commu-nication medium. LoRa provides for this reason a rangeof communication options (centre frequency, spreading fac-tor, bandwidth, coding rates) from which a transmitter canchoose. Many combination settings are orthogonal and pro-vide simultaneous collision free communications. Neverthe-less, there is a limit regarding the number of transmitters aLoRa system can support. In this paper we investigate thecapacity limits of LoRa networks. Using experiments wedevelop models describing LoRa communication behaviour.We use these models to parameterise a LoRa simulation tostudy scalability. Our experiments show that a typical smartcity deployment can support 120 nodes per 3.8 ha, which isnot sucient for future IoT deployments. LoRa networkscan scale quite well, however, if they use dynamic commu-nication parameter selection and/or multiple sinks.

  • 26.
    Borgström, Gustaf
    et al.
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    Sembrant, Andreas
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    Black-Schaffer, David
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    Adaptive cache warming for faster simulations2017Ingår i: Proc. 9th Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, New York: ACM Press, 2017, artikel-id 1Konferensbidrag (Refereegranskat)
  • 27.
    Cambazoglu, Volkan
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Avdelningen för datorteknik. Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    Protocol, mobility and adversary models for the verification of security2016Licentiatavhandling, sammanläggning (Övrigt vetenskapligt)
    Abstract [en]

    The increasing heterogeneity of communicating devices, ranging from resource constrained battery driven sensor nodes to multi-core processor computers, challenges protocol design. We examine security and privacy protocols with respect to exterior factors such as users, adversaries, and computing and communication resources; and also interior factors such as the operations, the interactions and the parameters of a protocol.

    Users and adversaries interact with security and privacy protocols, and even affect the outcome of the protocols. We propose user mobility and adversary models to examine how the location privacy of users is affected when they move relative to each other in specific patterns while adversaries with varying strengths try to identify the users based on their historical locations. The location privacy of the users are simulated with the support of the K-Anonymity protection mechanism, the Distortion-based metric, and our models of users' mobility patterns and adversaries' knowledge about users.

    Security and privacy protocols need to operate on various computing and communication resources. Some of these protocols can be adjusted for different situations by changing parameters. A common example is to use longer secret keys in encryption for stronger security. We experiment with the trade-off between the security and the performance of the Fiat–Shamir identification protocol. We pipeline the protocol to increase its utilisation as the communication delay outweighs the computation.

    A mathematical specification based on a formal method leads to a strong proof of security. We use three formal languages with their tool supports in order to model and verify the Secure Hierarchical In-Network Aggregation (SHIA) protocol for Wireless Sensor Networks (WSNs). The three formal languages specialise on cryptographic operations, distributed systems and mobile processes. Finding an appropriate level of abstraction to represent the essential features of the protocol in three formal languages was central.

    Delarbeten
    1. The impact of trace and adversary models on location privacy provided by K-anonymity
    Öppna denna publikation i ny flik eller fönster >>The impact of trace and adversary models on location privacy provided by K-anonymity
    2012 (Engelska)Ingår i: Proc. 1st Workshop on Measurement, Privacy, and Mobility, New York: ACM Press, 2012, artikel-id 6Konferensbidrag, Publicerat paper (Refereegranskat)
    Ort, förlag, år, upplaga, sidor
    New York: ACM Press, 2012
    Nationell ämneskategori
    Datavetenskap (datalogi)
    Forskningsämne
    Datavetenskap med inriktning mot datorkommunikation
    Identifikatorer
    urn:nbn:se:uu:diva-171581 (URN)10.1145/2181196.2181202 (DOI)978-1-4503-1163-2 (ISBN)
    Konferens
    MPM 2012
    Projekt
    ProFuNWISENET
    Tillgänglig från: 2012-04-10 Skapad: 2012-03-22 Senast uppdaterad: 2018-01-12Bibliografiskt granskad
    2. Towards adaptive zero-knowledge protocols: A case study with Fiat–Shamir identification protocol
    Öppna denna publikation i ny flik eller fönster >>Towards adaptive zero-knowledge protocols: A case study with Fiat–Shamir identification protocol
    2013 (Engelska)Ingår i: Proc. 9th Swedish National Computer Networking Workshop, 2013, s. 67-70Konferensbidrag, Publicerat paper (Refereegranskat)
    Abstract [en]

    Interactive zero-knowledge protocols are used as identification protocols. The protocols are executed in rounds, with security being increased with every round. This allows for a trade-off between security and performance to adapt the protocol to the requirements of the scenario. We experimentally investigate the Fiat–Shamir identification protocol on machines and networks with different performance characteristics. We find that the delay of the protocol highly depends on network latency and upload bandwidth. Computation time becomes more visible, when the protocol transmits little amount of data via a low latency network. We also experience that the impact of the sizes of the variables on the delay of the protocol is less than the number of rounds', which are interior factors in the protocol.

    Nationell ämneskategori
    Datavetenskap (datalogi)
    Forskningsämne
    Datavetenskap med inriktning mot datorkommunikation
    Identifikatorer
    urn:nbn:se:uu:diva-201070 (URN)
    Konferens
    SNCNW 2013
    Projekt
    WISENETProFuN
    Tillgänglig från: 2013-06-05 Skapad: 2013-06-05 Senast uppdaterad: 2018-01-11Bibliografiskt granskad
    3. Modelling and analysing a WSN secure aggregation protocol: A comparison of languages and tool support
    Öppna denna publikation i ny flik eller fönster >>Modelling and analysing a WSN secure aggregation protocol: A comparison of languages and tool support
    2015 (Engelska)Rapport (Övrigt vetenskapligt)
    Serie
    Technical report / Department of Information Technology, Uppsala University, ISSN 1404-3203 ; 2015-033
    Nationell ämneskategori
    Datavetenskap (datalogi) Kommunikationssystem
    Forskningsämne
    Datavetenskap med inriktning mot datorkommunikation
    Identifikatorer
    urn:nbn:se:uu:diva-268453 (URN)
    Projekt
    ProFuN
    Forskningsfinansiär
    Stiftelsen för strategisk forskning (SSF), RIT08-0065
    Tillgänglig från: 2015-12-03 Skapad: 2015-12-04 Senast uppdaterad: 2018-01-10Bibliografiskt granskad
  • 28.
    Cambazoglu, Volkan
    et al.
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    Gutkovas, Ramunas
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datalogi.
    Åman Pohjola, Johannes
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datalogi.
    Victor, Björn
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datalogi.
    Modelling and analysing a WSN secure aggregation protocol: A comparison of languages and tool support2015Rapport (Övrigt vetenskapligt)
  • 29.
    Carlos, Perez Penichet
    et al.
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    Hermans, Frederik
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    Varshney, Ambuj
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    Voigt, Thiemo
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    Augmenting IoT networks with backscatter-enabled passive sensor tags2016Ingår i: Proceedings of the 3rd Workshop on Hot Topics in Wireless, 2016, s. 23-27Konferensbidrag (Refereegranskat)
    Abstract [en]

    The sensing modalities available in an Internet-of-Things (IoT) network are usually fixed before deployment, when the operator selects a suitable IoT platform. Retrofitting a deployment with additional sensors can be cumbersome, because it requires either modifying the deployed hardware or adding new devices that then have to be maintained. In this paper, we present our vision and work towards passive sensor tags: battery-free devices that allow to augment existing IoT deployments with additional sensing capabilities without the need to modify the existing deployment. Our passive sensor tags use backscatter transmissions to communicate with the deployed network. Crucially, they do this in a way that is compatible with the deployed network's radio protocol, and without the need for additional infrastructure. We present an FPGA-based prototype of a passive sensor tag that can communicate with unmodified 802.15.4 IoT devices. Our initial experiments with the prototype support the feasibility of our approach. We also lay out the next steps towards fully realizing the vision of passive sensor tags.

  • 30.
    Carlos, Perez Penichet
    et al.
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    Noda, Claro
    Mid-Sweden University, Sweden.
    Varshney, Ambuj
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    Voigt, Thiemo
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    Battery-free 802.15. 4 Receiver2018Ingår i: 7th ACM/IEEE International Conference on Information Processing in Sensor Networks (IPSN), IEEE, 2018Konferensbidrag (Refereegranskat)
    Abstract [en]

    We present the architecture of an 802.15.4 receiver that, for the first time, operates at a few hundred microwatts, enabling new battery-free applications. To reach the required micro-power consumption, the architecture diverges from that of commodity receivers in two important ways. First, it offloads the power-hungry local oscillator to an external device, much like backscatter transmitters do. Second, we avoid the energy cost of demodulating a phase-modulated signal by treating 802.15.4 as a frequency-modulated one, which allows us to receive with a simple passive detector and an energy-efficient thresholding circuit. We describe a prototype that can receive 802.15.4 frames with a power consumption of 361 μW. Our receiver prototype achieves sufficient communication range to integrate with deployed wireless sensor networks (WSNs). We illustrate this integration by pairing the prototype with an 802.15.4 backscatter transmitter and integrating it with unmodified 802.15.4 sensor nodes running the TSCH and Glossy protocols.

  • 31.
    Carlos, Perez Penichet
    et al.
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    Noda, Claro
    Mid-Sweden University, Sweden.
    Varshney, Ambuj
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    Voigt, Thiemo
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    Demo Abstract: Battery-Free 802.15.4 Receiver2018Ingår i: 17th ACM/IEEE International Conference on Information Processing in Sensor Networks (IPSN), IEEE, 2018, s. 130-131Konferensbidrag (Refereegranskat)
    Abstract [en]

    We present the architecture for an 802.15.4 receiver that enables battery-free operation. To reach micro-power consumption, the architecture diverges from that of commodity receivers in the following ways: First, similar to backscatter transmitters, it offloads the power-hungry local oscillator to an external device. Second, we avoid the energy cost of demodulating a phase-modulated signal by treating 802.15.4 as a frequency-modulated one, allowing us to receive with a simple passive detector and an energy-efficient thresholding circuit. We demonstrate an off-the-shelf prototype of our receiver receives 802.15.4 from a distance of 470 cm with the carrier generator 30 cm away. This range is sufficient to integrate with deployed wireless sensor networks (WSNs). We demonstrate this integration by pairing our receiver with a 802.15.4 backscatter transmitter and integrating it with unmodified commodity sensor nodes running the TSCH protocol.

  • 32.
    Carlos, Perez Penichet
    et al.
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation. Uppsala Univ, Uppsala, Sweden.
    Voigt, Thiemo
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorteknik. RISE SICS, Lulea, Sweden.
    Carrier Scheduling in IoT Networks with Interoperable Battery-free Backscatter Tags2019Ingår i: IPSN '19: Proceedings of the 2019 International Conference on Information Processing in Sensor Networks, Association for Computing Machinery (ACM), 2019, s. 329-330Konferensbidrag (Refereegranskat)
    Abstract [en]

    New battery-free backscatter tags that integrate with unmodified standard IoT devices can extend the latter's sensing capabilities in a scalable and cost effective way. Existing IoT nodes can provide the unmodulated carrier needed by the new nodes, avoiding the need for additional infrastructure. This, however, puts extra energetic demands on constrained IoT nodes while increasing interference and contention in the network. We use a slotted MAC protocol to guarantee synchronization between transmitters, receivers and carrier generators. We then express the slot allocation problem as a Constraint Optimization Problem (COP) that parallelizes interrogations to battery-free tags when they do not collide with each other and reuses carriers for multiple tags looking to minimize the total time and the number of carrier generators needed to interrogate a set of tags. In networks with sufficient battery-free nodes we obtain a 25% reduction in the number of necessary carriers and a 50% decrease in interrogation time in most cases; leading to significant energy savings, reduced collisions and improved latency.

  • 33.
    Carlos, Pérez Penichet
    et al.
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    Hermans, Frederik
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    Voigt, Thiemo
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    On Limits of Constructive Interference in Backscatter Systems2017Ingår i: Global Internet of Things Summit (GIoTS), 2017, IEEE, 2017, s. 178-182Konferensbidrag (Övrigt vetenskapligt)
    Abstract [en]

    Backscatter communication reduces the energy consumption of resource-constrained sensors and actuators by several orders of magnitude as it avoids the resource-consuming need to generate a radio wave. Many backscatter systems and applications suffer from low communication range. By exploiting the collective power of several tags that transmit the same data simultaneously, constructive interference may help to remedy this problem and increase the communication range. When several tags backscatter the same signal simultaneously it is not necessarily true that constructive interference occurs. As our theoretical results and previous work indicate the interference might also be destructive. Our experimental results on real hardware suggest that exploiting constructive interference to increase the communication range requires careful coordination which is difficult in decentralized settings.

  • 34.
    Carlson, Trevor E.
    et al.
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    Heirman, Wim
    Intel, ExaSci Lab, Santa Clara, CA USA..
    Allam, Osman
    Univ Ghent, B-9000 Ghent, Belgium..
    Kaxiras, Stefanos
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    Eeckhout, Lieven
    Univ Ghent, B-9000 Ghent, Belgium..
    The Load Slice Core Microarchitecture2015Ingår i: 2015 ACM/IEEE 42Nd Annual International Symposium On Computer Architecture (ISCA), 2015, s. 272-284Konferensbidrag (Refereegranskat)
    Abstract [en]

    Driven by the motivation to expose instruction-level parallelism (ILP), microprocessor cores have evolved from simple, in-order pipelines into complex, superscalar out-of-order designs. By extracting ILP, these processors also enable parallel cache and memory operations as a useful side-effect. Today, however, the growing off-chip memory wall and complex cache hierarchies of many-core processors make cache and memory accesses ever more costly. This increases the importance of extracting memory hierarchy parallelism (MHP), while reducing the net impact of more general, yet complex and power-hungry ILP-extraction techniques. In addition, for multi-core processors operating in power- and energy-constrained environments, energy-efficiency has largely replaced single-thread performance as the primary concern. Based on this observation, we propose a core microarchitecture that is aimed squarely at generating parallel accesses to the memory hierarchy while maximizing energy efficiency. The Load Slice Core extends the efficient in-order, stall-on-use core with a second in-order pipeline that enables memory accesses and address-generating instructions to bypass stalled instructions in the main pipeline. Backward program slices containing address-generating instructions leading up to loads and stores are extracted automatically by the hardware, using a novel iterative algorithm that requires no software support or recompilation. On average, the Load Slice Core improves performance over a baseline in-order processor by 53% with overheads of only 15% in area and 22% in power, leading to an increase in energy efficiency (MIPS/Watt) over in-order and out-of-order designs by 43% and over 4.7x, respectively. In addition, for a power- and area-constrained many-core design, the Load Slice Core outperforms both in-order and out-of-order designs, achieving a 53% and 95% higher performance, respectively, thus providing an alternative direction for future many-core processors.

  • 35.
    Carlson, Trevor E.
    et al.
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    Tran, Kim-Anh
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    Jimborean, Alexandra
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    Koukos, Konstantinos
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    Själander, Magnus
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    Kaxiras, Stefanos
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    Transcending hardware limits with software out-of-order processing2017Ingår i: IEEE Computer Architecture Letters, ISSN 1556-6056, Vol. 16, nr 2, s. 162-165Artikel i tidskrift (Refereegranskat)
  • 36. Catalán Rivas, Victoria
    et al.
    Fröjd, Emil
    Holmberg, Tobias
    Ragnarsson, Felix
    Rick, Elsa
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    Corneo, Lorenzo
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    Varshney, Ambuj
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    Rohner, Christian
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    Voigt, Thiemo
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    Gunningberg, Per
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    Environmental Control at the Edge2018Konferensbidrag (Övrigt vetenskapligt)
  • 37.
    Ceballos, Germán
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    How to make tasks faster: Revealing the complex interactions of tasks in the memory system2017Ingår i: Proc. Companion 8th ACM International Conference on Systems, Programming, Languages, and Applications: Software for Humanity, New York: ACM Press, 2017, s. 1-3Konferensbidrag (Refereegranskat)
  • 38.
    Ceballos, Germán
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Avdelningen för datorteknik. Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    Modeling the interactions between tasks and the memory system2017Licentiatavhandling, sammanläggning (Övrigt vetenskapligt)
    Abstract [en]

    Making computer systems more energy efficient while obtaining the maximum performance possible is key for future developments in engineering, medicine, entertainment, etc. However it has become a difficult task due to the increasing complexity of hardware and software, and their interactions. For example, developers have to deal with deep, multi-level cache hierarchies on modern CPUs, and keep busy thousands of cores in GPUs, which makes the programming process more difficult.

    To simplify this task, new abstractions and programming models are becoming popular. Their goal is to make applications more scalable and efficient, while still providing the flexibility and portability of old, widely adopted models. One example of this is task-based programming, where simple independent tasks (functions) are delegated to a runtime system which orchestrates their execution. This approach has been successful because the runtime can automatically distribute work across hardware cores and has the potential to minimize data movement and placement (e.g., being aware of the cache hierarchy).

    To build better runtime systems, it is crucial to understand bottlenecks in the performance of current and future multicore systems. In this thesis, we provide fast, accurate and mathematically-sound models and techniques to understand the execution of task-based applications concerning three key aspects: memory behavior (data locality), scheduling, and performance. With these methods, we lay the groundwork for improving runtime system, providing insight into the interplay between the schedule's behavior, data reuse through the cache hierarchy, and the resulting performance.

    Delarbeten
    1. Shared Resource Sensitivity in Task-Based Runtime Systems
    Öppna denna publikation i ny flik eller fönster >>Shared Resource Sensitivity in Task-Based Runtime Systems
    2013 (Engelska)Ingår i: Proc. 6th Swedish Workshop on Multi-Core Computing, Halmstad University Press, 2013Konferensbidrag, Publicerat paper (Refereegranskat)
    Ort, förlag, år, upplaga, sidor
    Halmstad University Press, 2013
    Nationell ämneskategori
    Datorsystem
    Identifikatorer
    urn:nbn:se:uu:diva-212780 (URN)
    Konferens
    MCC13, November 25–26, Halmstad, Sweden
    Projekt
    Resource Sharing ModelingUPMARC
    Forskningsfinansiär
    Vetenskapsrådet
    Tillgänglig från: 2013-12-13 Skapad: 2013-12-13 Senast uppdaterad: 2018-11-16Bibliografiskt granskad
    2. Formalizing data locality in task parallel applications
    Öppna denna publikation i ny flik eller fönster >>Formalizing data locality in task parallel applications
    2016 (Engelska)Ingår i: Algorithms and Architectures for Parallel Processing, Springer, 2016, s. 43-61Konferensbidrag, Publicerat paper (Refereegranskat)
    Ort, förlag, år, upplaga, sidor
    Springer, 2016
    Serie
    Lecture Notes in Computer Science, ISSN 0302-9743 ; 10049
    Nationell ämneskategori
    Datavetenskap (datalogi)
    Identifikatorer
    urn:nbn:se:uu:diva-310341 (URN)10.1007/978-3-319-49956-7_4 (DOI)000389797000004 ()978-3-319-49955-0 (ISBN)
    Konferens
    ICA3PP 2016, December 14–16, Granada, Spain
    Projekt
    UPMARCResource Sharing Modeling
    Forskningsfinansiär
    Stiftelsen för strategisk forskning (SSF), FFL12-0051
    Tillgänglig från: 2016-11-19 Skapad: 2016-12-14 Senast uppdaterad: 2018-11-16Bibliografiskt granskad
    3. TaskInsight: Understanding task schedules effects on memory and performance
    Öppna denna publikation i ny flik eller fönster >>TaskInsight: Understanding task schedules effects on memory and performance
    2017 (Engelska)Ingår i: Proc. 8th International Workshop on Programming Models and Applications for Multicores and Manycores, New York: ACM Press, 2017, s. 11-20Konferensbidrag, Publicerat paper (Refereegranskat)
    Ort, förlag, år, upplaga, sidor
    New York: ACM Press, 2017
    Nationell ämneskategori
    Datorteknik
    Identifikatorer
    urn:nbn:se:uu:diva-315033 (URN)10.1145/3026937.3026943 (DOI)978-1-4503-4883-6 (ISBN)
    Konferens
    PMAM 2017, February 4–8, Austin, TX
    Projekt
    UPMARCResource Sharing Modeling
    Forskningsfinansiär
    VetenskapsrådetStiftelsen för strategisk forskning (SSF), FFL12-0051EU, Horisont 2020, 687698
    Tillgänglig från: 2017-02-04 Skapad: 2017-02-08 Senast uppdaterad: 2018-11-16Bibliografiskt granskad
    4. Analyzing performance variation of task schedulers with TaskInsight
    Öppna denna publikation i ny flik eller fönster >>Analyzing performance variation of task schedulers with TaskInsight
    2018 (Engelska)Ingår i: Parallel Computing, ISSN 0167-8191, E-ISSN 1872-7336, Vol. 75, s. 11-27Artikel i tidskrift (Refereegranskat) Published
    Nationell ämneskategori
    Datorteknik
    Identifikatorer
    urn:nbn:se:uu:diva-340202 (URN)10.1016/j.parco.2018.02.003 (DOI)000433655700002 ()
    Projekt
    UPMARCResource Sharing Modeling
    Forskningsfinansiär
    Vetenskapsrådet, FFL12-0051Stiftelsen för strategisk forskning (SSF), FFL12-0051
    Tillgänglig från: 2018-02-22 Skapad: 2018-01-26 Senast uppdaterad: 2018-11-16Bibliografiskt granskad
  • 39.
    Ceballos, Germán
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Avdelningen för datorteknik. Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation. Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorteknik.
    Understanding Task Parallelism: Providing insight into scheduling, memory, and performance for CPUs and Graphics2018Doktorsavhandling, sammanläggning (Övrigt vetenskapligt)
    Abstract [en]

    Maximizing the performance of computer systems while making them more energy efficient is vital for future developments in engineering, medicine, entertainment, etc. However, the increasing complexity of software, hardware, and their interactions makes this task difficult. Software developers have to deal with complex memory architectures such as multilevel caches on modern CPUs and keeping thousands of cores busy in GPUs, which makes the programming process harder.

    Task-based programming provides high-level abstractions to simplify the development process. In this model, independent tasks (functions) are submitted to a runtime system, which orchestrates their execution across hardware resources. This approach has become popular and successful because the runtime can distribute the workload across hardware resources automatically, and has the potential to optimize the execution to minimize data movement (e.g., being aware of the cache hierarchy).

    However, to build better runtime systems, we now need to understand bottlenecks in the performance of current and future multicore architectures. Unfortunately, since most current work was designed for sequential or thread-based workloads, there is an overall lack of tools and methods to gain insight about the execution of these applications, allowing both the runtime and the programmers to detect potential optimizations.

    In this thesis, we address this lack of tools by providing fast, accurate and mathematically-sound models to understand the execution of task-based applications. In particular, we center these models around three key aspects of the execution: memory behavior (data locality), scheduling, and performance. Our contributions provide insight into the interplay between the schedule's behavior, data reuse through the cache hierarchy, and the resulting performance. These contributions lay the groundwork for improving runtime systems. We first apply these methods to analyze a diverse set of CPU applications, and then leverage them to one of the most common workloads in current systems: graphics rendering on GPUs.

    Delarbeten
    1. Shared Resource Sensitivity in Task-Based Runtime Systems
    Öppna denna publikation i ny flik eller fönster >>Shared Resource Sensitivity in Task-Based Runtime Systems
    2013 (Engelska)Ingår i: Proc. 6th Swedish Workshop on Multi-Core Computing, Halmstad University Press, 2013Konferensbidrag, Publicerat paper (Refereegranskat)
    Ort, förlag, år, upplaga, sidor
    Halmstad University Press, 2013
    Nationell ämneskategori
    Datorsystem
    Identifikatorer
    urn:nbn:se:uu:diva-212780 (URN)
    Konferens
    MCC13, November 25–26, Halmstad, Sweden
    Projekt
    Resource Sharing ModelingUPMARC
    Forskningsfinansiär
    Vetenskapsrådet
    Tillgänglig från: 2013-12-13 Skapad: 2013-12-13 Senast uppdaterad: 2018-11-16Bibliografiskt granskad
    2. Formalizing data locality in task parallel applications
    Öppna denna publikation i ny flik eller fönster >>Formalizing data locality in task parallel applications
    2016 (Engelska)Ingår i: Algorithms and Architectures for Parallel Processing, Springer, 2016, s. 43-61Konferensbidrag, Publicerat paper (Refereegranskat)
    Ort, förlag, år, upplaga, sidor
    Springer, 2016
    Serie
    Lecture Notes in Computer Science, ISSN 0302-9743 ; 10049
    Nationell ämneskategori
    Datavetenskap (datalogi)
    Identifikatorer
    urn:nbn:se:uu:diva-310341 (URN)10.1007/978-3-319-49956-7_4 (DOI)000389797000004 ()978-3-319-49955-0 (ISBN)
    Konferens
    ICA3PP 2016, December 14–16, Granada, Spain
    Projekt
    UPMARCResource Sharing Modeling
    Forskningsfinansiär
    Stiftelsen för strategisk forskning (SSF), FFL12-0051
    Tillgänglig från: 2016-11-19 Skapad: 2016-12-14 Senast uppdaterad: 2018-11-16Bibliografiskt granskad
    3. Analyzing performance variation of task schedulers with TaskInsight
    Öppna denna publikation i ny flik eller fönster >>Analyzing performance variation of task schedulers with TaskInsight
    2018 (Engelska)Ingår i: Parallel Computing, ISSN 0167-8191, E-ISSN 1872-7336, Vol. 75, s. 11-27Artikel i tidskrift (Refereegranskat) Published
    Nationell ämneskategori
    Datorteknik
    Identifikatorer
    urn:nbn:se:uu:diva-340202 (URN)10.1016/j.parco.2018.02.003 (DOI)000433655700002 ()
    Projekt
    UPMARCResource Sharing Modeling
    Forskningsfinansiär
    Vetenskapsrådet, FFL12-0051Stiftelsen för strategisk forskning (SSF), FFL12-0051
    Tillgänglig från: 2018-02-22 Skapad: 2018-01-26 Senast uppdaterad: 2018-11-16Bibliografiskt granskad
    4. Behind the Scenes: Memory Analysis of Graphical Workloads on Tile-based GPUs
    Öppna denna publikation i ny flik eller fönster >>Behind the Scenes: Memory Analysis of Graphical Workloads on Tile-based GPUs
    2018 (Engelska)Ingår i: Proc. International Symposium on Performance Analysis of Systems and Software: ISPASS 2018, IEEE Computer Society, 2018, s. 1-11Konferensbidrag, Publicerat paper (Refereegranskat)
    Ort, förlag, år, upplaga, sidor
    IEEE Computer Society, 2018
    Nationell ämneskategori
    Datorsystem
    Identifikatorer
    urn:nbn:se:uu:diva-361214 (URN)10.1109/ISPASS.2018.00009 (DOI)978-1-5386-5010-3 (ISBN)
    Konferens
    ISPASS 2018, April 2–4, Belfast, UK
    Projekt
    UPMARC
    Tillgänglig från: 2018-09-21 Skapad: 2018-09-21 Senast uppdaterad: 2018-11-16Bibliografiskt granskad
    5. Tail-PASS: Resource-based Cache Management for Tiled Graphics Rendering Hardware
    Öppna denna publikation i ny flik eller fönster >>Tail-PASS: Resource-based Cache Management for Tiled Graphics Rendering Hardware
    2018 (Engelska)Ingår i: Proc. 16th International Conference on Parallel and Distributed Processing with Applications, IEEE, 2018, s. 55-63Konferensbidrag, Publicerat paper (Refereegranskat)
    Abstract [en]

    Modern graphics rendering is a very expensive process and can account for 60% of the battery consumption on current games. Much of the cost comes from the high memory bandwidth of rendering complex graphics. To render a frame, multiple smaller rendering passes called scenes are executed, with each one tiled for parallel execution. The data for each scene comes from hundreds of software resources (textures). We observe that each frame can consume up to 1000s of MB of data, but that over 75% of the graphics memory accesses are to the top-10 resources, and that bypassing the remaining infrequently accessed (tail) resources reduces cache pollution. Bypassing the tail can save up to 35% of the main memory traffic over resource-oblivious replacement policies and cache management techniques. In this paper, we propose Tail-PASS, a cache management technique that detects the most accessed resources at runtime, learns if it is worth bypassing the least accessed ones, and then dynamically enables/disables bypassing to reduce cache pollution on a per-scene basis. Overall, we see an average reduction in bandwidth-per-frame of 22% (up to 46%) by bypassing all but the top-10 resources and an 11% (up to 44%) reduction if only the top-2 resources are cached.

    Ort, förlag, år, upplaga, sidor
    IEEE, 2018
    Nationell ämneskategori
    Datorsystem Datavetenskap (datalogi)
    Identifikatorer
    urn:nbn:se:uu:diva-363920 (URN)10.1109/BDCloud.2018.00022 (DOI)000467843200008 ()978-1-7281-1141-4 (ISBN)
    Konferens
    ISPA 2018, December 11–13, Melbourne, Australia
    Forskningsfinansiär
    EU, Europeiska forskningsrådet, 715283
    Tillgänglig från: 2018-10-21 Skapad: 2018-10-21 Senast uppdaterad: 2019-06-17Bibliografiskt granskad
  • 40.
    Ceballos, Germán
    et al.
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    Black-Schaffer, David
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    Spatial and Temporal Cache Sharing Analysis in Tasks2016Konferensbidrag (Övrigt vetenskapligt)
  • 41.
    Ceballos, Germán
    et al.
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    Grass, Thomas
    Black-Schaffer, David
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    Hugo, Andra
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    Characterizing Task Scheduling Performance Based on Data Reuse2016Ingår i: Proc. 9th Nordic Workshop on Multi-Core Computing, 2016Konferensbidrag (Refereegranskat)
  • 42.
    Ceballos, Germán
    et al.
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    Grass, Thomas
    Hugo, Andra
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    Black-Schaffer, David
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    Analyzing performance variation of task schedulers with TaskInsight2018Ingår i: Parallel Computing, ISSN 0167-8191, E-ISSN 1872-7336, Vol. 75, s. 11-27Artikel i tidskrift (Refereegranskat)
  • 43.
    Ceballos, Germán
    et al.
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    Grass, Thomas
    Hugo, Andra
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    Black-Schaffer, David
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    TaskInsight: Understanding task schedules effects on memory and performance2017Ingår i: Proc. 8th International Workshop on Programming Models and Applications for Multicores and Manycores, New York: ACM Press, 2017, s. 11-20Konferensbidrag (Refereegranskat)
  • 44.
    Ceballos, Germán
    et al.
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    Hagersten, Erik
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    Black-Schaffer, David
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    Formalizing data locality in task parallel applications2016Ingår i: Algorithms and Architectures for Parallel Processing, Springer, 2016, s. 43-61Konferensbidrag (Refereegranskat)
  • 45.
    Ceballos, Germán
    et al.
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    Hagersten, Erik
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    Black-Schaffer, David
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    StatTask: Reuse distance analysis for task-based applications2015Ingår i: Proc. 7th Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, New York: ACM Press, 2015, s. 1-7Konferensbidrag (Refereegranskat)
  • 46.
    Ceballos, Germán
    et al.
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    Hagersten, Erik
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    Black-Schaffer, David
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    Tail-PASS: Resource-based Cache Management for Tiled Graphics Rendering Hardware2018Ingår i: Proc. 16th International Conference on Parallel and Distributed Processing with Applications, IEEE, 2018, s. 55-63Konferensbidrag (Refereegranskat)
    Abstract [en]

    Modern graphics rendering is a very expensive process and can account for 60% of the battery consumption on current games. Much of the cost comes from the high memory bandwidth of rendering complex graphics. To render a frame, multiple smaller rendering passes called scenes are executed, with each one tiled for parallel execution. The data for each scene comes from hundreds of software resources (textures). We observe that each frame can consume up to 1000s of MB of data, but that over 75% of the graphics memory accesses are to the top-10 resources, and that bypassing the remaining infrequently accessed (tail) resources reduces cache pollution. Bypassing the tail can save up to 35% of the main memory traffic over resource-oblivious replacement policies and cache management techniques. In this paper, we propose Tail-PASS, a cache management technique that detects the most accessed resources at runtime, learns if it is worth bypassing the least accessed ones, and then dynamically enables/disables bypassing to reduce cache pollution on a per-scene basis. Overall, we see an average reduction in bandwidth-per-frame of 22% (up to 46%) by bypassing all but the top-10 resources and an 11% (up to 44%) reduction if only the top-2 resources are cached.

  • 47.
    Ceballos, Germán
    et al.
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    Hagersten, Erik
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    Black-Schaffer, David
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    Understanding the interplay between task scheduling, memory and performance2017Ingår i: Proc. Companion 8th ACM International Conference on Systems, Programming, Languages, and Applications: Software for Humanity, New York: ACM Press, 2017, s. 21-23Konferensbidrag (Refereegranskat)
  • 48.
    Ceballos, Germán
    et al.
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    Hugo, Andra
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    Hagersten, Erik
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    Black-Schaffer, David
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    Exploring scheduling effects on task performance with TaskInsight2017Ingår i: Supercomputing frontiers and innovations, ISSN 2214-3270, E-ISSN 2313-8734, Vol. 4, nr 3, s. 91-98Artikel i tidskrift (Refereegranskat)
  • 49.
    Ceballos, Germán
    et al.
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    Sembrant, Andreas
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    Carlson, Trevor E.
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    Black-Schaffer, David
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    Analyzing Graphics Workloads on Tile-based GPUs2017Ingår i: Proc. 20th International Symposium on Workload Characterization, IEEE, 2017, s. 108-109Konferensbidrag (Refereegranskat)
  • 50.
    Ceballos, Germán
    et al.
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    Sembrant, Andreas
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    Carlson, Trevor E.
    Black-Schaffer, David
    Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
    Behind the Scenes: Memory Analysis of Graphical Workloads on Tile-based GPUs2018Ingår i: Proc. International Symposium on Performance Analysis of Systems and Software: ISPASS 2018, IEEE Computer Society, 2018, s. 1-11Konferensbidrag (Refereegranskat)
12345 1 - 50 av 211
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