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  • 251. McDermott, Roger
    et al.
    Zarb, Mark
    Daniels, Mats
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
    Isomöttönen, Ville
    First year computing students' perceptions of authenticity in assessment2017In: Proc. 22nd Conference on Innovation and Technology in Computer Science Education, New York: ACM Press, 2017, p. 10-15Conference paper (Refereed)
  • 252. McDermott, Roger
    et al.
    Zarb, Mark
    Daniels, Mats
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
    Nylén, Aletta
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computing Science.
    Pears, Arnold
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
    Isomöttönen, Ville
    Caspersen, Michael
    The authenticity of 'authentic' assessment: Some faculty perceptions2017In: Proc. 47th ASEE/IEEE Frontiers in Education Conference, Piscataway, NJ: IEEE Press, 2017Conference paper (Refereed)
  • 253.
    McNamara, Liam
    et al.
    Swedish Inst Comp Sci, SE-16451 Stockholm, Sweden.
    Ngai, Edith
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
    SADHealth: A personal mobile sensing system for seasonal health monitoring2018In: IEEE Systems Journal, ISSN 1932-8184, E-ISSN 1937-9234, Vol. 12, no 1, p. 30-40Article in journal (Refereed)
    Abstract [en]

    People's health, mood, and activities are closely related to their environment and the seasons. Countries at extreme latitudes (e.g., Sweden, U.K., and Norway) experience huge variations in their light levels, impacting the population's mental state, well-being and energy levels. Advanced sensing technologies on smartphones enable nonintrusive and longitudinal monitoring of user states. The collected data make it possible for healthcare professionals and individuals to diagnose and rectify problems caused by seasonality. In this paper, we present a personal mobile sensing system that exploits technologies on smartphones to efficiently and accurately detect the light exposure, mood, and activity levels of individuals. We conducted a 2-year experiment with many users to test the functionality and performance of our system. The results show that we can obtain accurate light exposure estimation by opportunistically measuring light data on smartphones, tracking both personal light exposure and the general seasonal trends. An optional questionnaire also provides insight into the correlation between a user's mood and energy level. Our system is able to inform users how little light they are experiencing in the winter time. It can also correlate light exposure data with reduced mood and energy, and provide quantitative measurements for lifestyle changes.

  • 254.
    Melin, Karin
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
    The GDPR Compliance of Blockchain: A qualitative study on regulating innovative technology2019Independent thesis Advanced level (professional degree), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    This thesis aims to explore the compliance of blockchain technology and the GDPR. The GDPR was implemented for the EU member states in May 2018 with the purpose of harmonizing data protection regulation. However, the regulation is based on the notion that data is stored and processed in a centralized system. This causes an issue when it comes to distributed networks, and in particular with the distributed ledger technology (DLT), the underlying technology of blockchain.

    For this thesis, a literature review has been conducted to investigate the problems of GDPR compliance for blockchain projects, and what technical solutions exist to make a blockchain solution more GDPR compliant. In addition, interviews have been conducted to investigate the technical and legal perspectives on the current and future situations of regulation and technology.

    Compatibility problems mainly concern the immutability and transparency of a blockchain and examples of technical solutions that handle those problems can be found in the literature. Nevertheless, none of the discussed solutions are yet to guarantee full GDPR compliance. The technical and legal perspectives share ideas of the main compliance issues. However, differences such as interpretation of technical details can be identified, indicating problems to arise when regulating blockchains in the future. Further interdisciplinary work on guidelines for the GDPR is necessary for blockchain projects to be successful in complying with the regulation as well as to strengthen the technology neutrality of the GDPR.

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  • 255.
    Melot, Nicolas
    et al.
    Linkoping Univ, Linkoping, Sweden..
    Janzén, Johan
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
    Kessler, Christoph
    Linkoping Univ, Linkoping, Sweden..
    Mimer and Schedeval: Tools for Comparing Static Schedulers for Streaming Applications on Manycore Architectures2015In: 2015 44Th International Conference On Parallel Processing Workshops, 2015, p. 146-155Conference paper (Refereed)
    Abstract [en]

    Scheduling algorithms published in the scientific literature are often difficult to evaluate or compare due to differences between the experimental evaluations in any two papers on the topic. Very few researchers share the details about the scheduling problem instances they use in their evaluation section, the code that allows them to transform the numbers they collect into the results and graphs they show, nor the raw data produced in their experiments. Also, many scheduling algorithms published are not tested against a real processor architecture to evaluate their efficiency in a realistic setting. In this paper, we describe Mimer, a modular evaluation tool-chain for static schedulers that enables the sharing of evaluation and analysis tools employed to elaborate scheduling papers. We propose Schedeval that integrates into Mimer to evaluate static schedules of streaming applications under throughput constraints on actual target execution platforms. We evaluate the performance of Schedeval at running streaming applications on the Intel Single-Chip Cloud computer (SCC), and we demonstrate the usefulness of our tool-chain to compare existing scheduling algorithms. We conclude that Mimer and Schedeval are useful tools to study static scheduling and to observe the behavior of streaming applications when running on manycore architectures.

  • 256.
    Mobyen, Uddin Ahmed
    et al.
    MdH.
    Fotouhi, Hossein
    MdH.
    Köckemann, Uwe
    Örebro University.
    Linden, Maria
    MdH.
    Tomasic, Ivan
    MdH.
    Tsiftes, Nicolas
    RISE SICS.
    Voigt, Thiemo
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
    Run-Time Assurance for the E-care@ home System2018Conference paper (Refereed)
  • 257.
    Mohaqeqi, Morteza
    et al.
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
    Abdullah, Jakaria
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
    Ekberg, Pontus
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
    Yi, Wang
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
    Refinement of workload models for engine controllers by state space partitioning2017In: 29th Euromicro Conference on Real-Time Systems: ECRTS 2017, Dagstuhl, Germany: Leibniz-Zentrum für Informatik , 2017, p. 11:1-22Conference paper (Refereed)
  • 258.
    Mohaqeqi, Morteza
    et al.
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
    Abdullah, Jakaria
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
    Guan, Nan
    Yi, Wang
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
    Schedulability analysis of synchronous digraph real-time tasks2016In: Proc. 28th Euromicro Conference on Real-Time Systems, IEEE Computer Society, 2016, p. 176-186Conference paper (Refereed)
  • 259.
    Mohaqeqi, Morteza
    et al.
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
    Abdullah, Jakaria
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
    Yi, Wang
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
    An executable semantics for synchronous task graphs: From SDRT to Ada2017In: Reliable Software Technologies — Ada-Europe 2017, Springer, 2017, Vol. 10300, p. 137-152Conference paper (Refereed)
    Abstract [en]

    We study a graph-based real-time task model in which inter-task synchronization can be specified through a rendezvous mechanism. Previously, efficient methods have been proposed for timing analysis of the corresponding task sets. In this paper, we first formally specify an operational semantics for the model. Next, we describe a method for Ada code generation for a set of such task graphs. We also specify extensions of the approach to cover a notion of broadcasting, as well as global inter-release separation time of real-time jobs. We have implemented the proposed method in a graphical tool which facilitates a model-based design and implementation of real-time software.

  • 260.
    Mohaqeqi, Morteza
    et al.
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
    Abdullah, Jakaria
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
    Yi, Wang
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
    Modeling and analysis of data flow graphs using the digraph real-time task model2016In: Reliable Software Technologies — Ada-Europe 2016, Springer, 2016, p. 15-29Conference paper (Refereed)
  • 261.
    Mohaqeqi, Morteza
    et al.
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
    Ekberg, Pontus
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
    Yi, Wang
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
    On fixed-priority schedulability analysis of sporadic tasks with self-suspension2016In: Proc. 24th International Conference on Real-Time Networks and Systems, New York: ACM Press, 2016, p. 109-118Conference paper (Refereed)
  • 262.
    Mohaqeqi, Morteza
    et al.
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
    Mousavi, Mohammad Reza
    Sound test-suites for cyber-physical systems2016In: Proc. 10th International Symposium on Theoretical Aspects of Software Engineering, IEEE Computer Society, 2016, p. 42-48Conference paper (Refereed)
  • 263.
    Mohaqeqi, Morteza
    et al.
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
    Mousavi, Mohammad Reza
    Towards an approximate conformance relation for hybrid I/O automata2016In: Proc. 1st Workshop on Verification and Validation of Cyber-Physical Systems, Open Publishing Association , 2016, p. 53-64Conference paper (Refereed)
  • 264.
    Mohaqeqi, Morteza
    et al.
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
    Nasri, Mitra
    Xu, Yang
    Cervin, Anton
    Årzén, Karl-Erik
    On the problem of finding optimal harmonic periods2016In: Proc. 24th International Conference on Real-Time Networks and Systems, New York: ACM Press, 2016, p. 171-180Conference paper (Refereed)
  • 265.
    Mohaqeqi, Morteza
    et al.
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
    Nasri, Mitra
    Max Planck Institute for Software Systems (MPI-SWS), Germany.
    Xu, Yang
    Department of Automatic Control, Lund University, Sweden.
    Cervin, Anton
    Department of Automatic Control, Lund University, Sweden.
    Årzén, Karl-Erik
    Department of Automatic Control, Lund University, Sweden.
    Optimal harmonic period assignment: complexity results and approximation algorithms2018In: Real-time systems, ISSN 0922-6443, E-ISSN 1573-1383, Vol. 54, no 4, p. 830-860Article in journal (Refereed)
    Abstract [en]

    Harmonic periods have wide applicability in industrial real-time systems. Rate monotonic (RM) is able to schedule task sets with harmonic periods up to 100% utilization. Also, if there is no release jitter and execution time variation, RM and EDF generate the same schedule for each instance of a task. As a result, all instances of a task are interfered by the same amount of workload. This property decreases the jitters that happen during sampling and actuation of the tasks, and hence, it increases the quality of service in control systems. In this paper, we consider the problem of optimal period assignment where the periods are constrained to be harmonic and the task set is required to be feasible. We study two variants of this problem. In the first one, the objective is to maximize the system utilization, while in the second one, the goal is to minimize the total weighted sum of the periods. First, we assume that an interval is determined a priori for each task from which its period can be selected. We show that both variants of the problem are (at least) weakly NP-hard. This is shown by reducing the NP-complete number partitioning problem to the mentioned harmonic period assignment problems. Afterwards, we consider a variant of the second problem in which the periods are not restricted to a special interval. We present two approximation algorithms with polynomial-time complexity for this problem and show that the maximum relative error of these algorithms is bounded by a factor of 1.125. Our evaluations show that, on the average, results of the approximation algorithms are very close to an optimal solution.

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    fulltext
  • 266.
    Mottola, Luca
    et al.
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication. RISE Swedish Institute of Computer Science, Kista SE164 29, Sweden;Politecnico di Milano, Milano 20133, Italy.
    Picco, Gian Pietro
    University of Trento, Trento 38122, Italy.
    Oppermann, Felix
    Graz University of Technology, Ultimo, NSW 2007, Australia.
    Eriksson, Joakim
    RISE Swedish Institute of Computer Science, Kista SE164 29, Sweden SICS.
    Finne, Niclas
    RISE Swedish Institute of Computer Science, Kista SE164 29, Sweden SICS.
    Fuchs, Harald
    SAP, Walldorf, 69190, Germany.
    Gaglione, Andrea
    University of Trento, Trento 38122, Italy.
    Karnouskos, Stamatis
    SAP, Walldorf, 69190, Germany.
    Montero, Patricio
    Acciona Infraestructuras S.A. Alcobendas, Madrid 28108, Spain.
    Oertel, Nina
    SAP, Walldorf, 69190, Germany.
    Römer, Kay
    Graz University of Technology, Ultimo, NSW 2007, Australia.
    Spiess, Patrik
    SAP, Walldorf, 69190, Germany.
    Tranquillini, Stefano
    University of Trento, Trento 38122, Italy.
    Voigt, Thiemo
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication. Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems. RISE Swedish Institute of Computer Science, Kista, SE-164 29, Sweden.
    makeSense: Simplifying the Integration of Wireless Sensor Networks into Business Processes2019In: IEEE Transactions on Software Engineering, ISSN 0098-5589, E-ISSN 1939-3520, Vol. 45, no 6, p. 576-596Article in journal (Refereed)
    Abstract [en]

    A wide gap exists between the state of the art in developing Wireless Sensor Network (WSN) software and current practices concerning the design, execution, and maintenance of business processes. WSN software is most often developed based on low-level OS abstractions, whereas business process development leverages high-level languages and tools. This state of affairs places WSNs at the fringe of industry. The makeSense system addresses this problem by simplifying the integration of WSNs into business processes. Developers use BPMN models extended with WSN-specific constructs to specify the application behavior across both traditional business process execution environments and the WSN itself, which is to be equipped with application-specific software. We compile these models into a high-level intermediate language—also directly usable by WSN developers—and then into OS-specific deployment-ready binaries. Key to this process is the notion of meta-abstraction, which we define to capture fundamental patterns of interaction with and within the WSN. The concrete realization of meta-abstractions is application-specific; developers tailor the system configuration by selecting concrete abstractions out of the existing codebase or by providing their own. Our evaluation of makeSense shows that i) users perceive our approach as a significant advance over the state of the art, providing evidence of the increased developer productivity when using makeSense; ii) in large-scale simulations, our prototype exhibits an acceptable system overhead and good scaling properties, demonstrating the general applicability of makeSense; and, iii) our prototype—including the complete tool-chain and underlying system support—sustains a real-world deployment where estimates by domain specialists indicate the potential for drastic reductions in the total cost of ownership compared to wired and conventional WSN-based solutions.

  • 267. Nasri, Mitra
    et al.
    Mohaqeqi, Morteza
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
    Fohler, Gerhard
    Quantifying the effect of period ratios on schedulability of rate monotonic2016In: Proc. 24th International Conference on Real-Time Networks and Systems, New York: ACM Press, 2016, p. 161-170Conference paper (Refereed)
  • 268.
    Nemitz, Catherine E.
    et al.
    Department of Computer Science, University of North Carolina at Chapel Hill.
    Yang, Kecheng
    Department of Computer Science, University of North Carolina at Chapel Hill.
    Yang, Ming
    Department of Computer Science, University of North Carolina at Chapel Hill.
    Ekberg, Pontus
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
    Anderson, James H.
    Department of Computer Science, University of North Carolina at Chapel Hill.
    Multiprocessor Real-Time Locking Protocols for Replicated Resources2016In: Proc. 28th Euromicro Conference on Real-Time Systems (ECRTS), 2016, p. 50-60Conference paper (Refereed)
    Abstract [en]

    A real-time multiprocessor synchronization problem is studied herein that has not be extensively studied before, namely, the management of replicated resources where tasks may require multiple replicas to execute. In prior work on replicated resources, k-exclusion locks have been used, but this restricts tasks to lock only one replica at a time. To motivate the need for unrestricted replica sharing, two use cases are discussed that reveal an interesting tradeoff: in one of the use cases, blocking is the dominant lock-related factor impacting schedulability, while in the other, lock/unlock overheads are. Motivated by these use cases, three replica-allocation protocols are presented. In the first two, the lock/unlock logic is very simple, yielding low overheads, but blocking is not optimal. In the third, blocking is optimal (ignoring constant factors), but additional lock/unlock overhead is incurred to properly order lock requests. Experiments are presented that examine the overhead/blocking tradeoff motivated by these protocols in some detail.

  • 269.
    Ngai, Edith C.-H.
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
    On providing sink anonymity for wireless sensor networks2016In: Security and Communication Networks, ISSN 1939-0114, E-ISSN 1939-0122, Vol. 9, no 2, p. 77-86Article in journal (Refereed)
  • 270.
    Ngai, Edith C.-H.
    et al.
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
    Brandauer, Stephan
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computing Science.
    Shrestha, Amendra
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
    Vandikas, Konstantinos
    Ericsson Res, Kista, Sweden..
    Personalized Mobile-Assisted Smart Transportation2016In: 2016 Digital Media Industry And Academic Forum (DMIAF), 2016, p. 158-160Conference paper (Refereed)
    Abstract [en]

    Digital media covers larger parts of our daily lives nowadays. Mobile services enable a better connected society where citizens can easily access public services, discover events, and obtain important information in the city. We observe the popularity of mobile car sharing applications, such as Uber and Didi Dache. Mobile social applications provide new ways of developing and optimizing public transportation. In this paper, we present a mobile platform for timetable-free traveling. It can capture the traffic demand of citizens in real-time, and support efficient planning and scheduling for vehicles on-demand. At the moment, the platform is targeted for public bus services, but it has great potential to be extended for self-driving vehicles in the future.

  • 271.
    Ngai, Edith
    et al.
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
    Dressler, Falko
    Univ Paderborn, Dept Comp Sci, D-33102 Paderborn, Germany.
    Leung, Victor
    Univ British Columbia, Vancouver, BC V6T 1Z4, Canada.
    Li, Mo
    Nanyang Technol Univ, Sch Comp Sci & Engn, Singapore 639798, Singapore.
    Guest Editorial Special Section on Internet-of-Things for Smart Cities and Urban Informatics2017In: IEEE Transactions on Industrial Informatics, ISSN 1551-3203, E-ISSN 1941-0050, Vol. 13, no 2, p. 748-750Article in journal (Other academic)
  • 272.
    Ngai, Edith
    et al.
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
    Ohlman, Börje
    Tsudik, Gene
    Uzun, Ersin
    Wählisch, Matthias
    Wood, Christopher A.
    Can we make a cake and eat it too?: A discussion of ICN security and privacy2017In: Computer communication review, ISSN 0146-4833, E-ISSN 1943-5819, Vol. 47, no 1, p. 49-54Article in journal (Other academic)
  • 273.
    Ngo, Tuan-Phong
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems. Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Division of Computer Systems.
    Model Checking of Software Systems under Weak Memory Models2019Doctoral thesis, comprehensive summary (Other academic)
    Abstract [en]

    When a program is compiled and run on a modern architecture, different optimizations may be applied to gain in efficiency. In particular, the access operations (e.g., read and write) to the shared memory may be performed in an out-of-order manner, i.e., in a different order than the order in which the operations have been issued by the program. The reordering of memory access operations leads to efficient use of instruction pipelines and thus an improvement in program execution times. However, the gain in this efficiency comes at a price. More precisely, programs running under modern architectures may exhibit unexpected behaviors by programmers. The out-of-order execution has led to the invention of new program semantics, called weak memory model (WMM). One crucial problem is to ensure the correctness of concurrent programs running under weak memory models.

    The thesis proposes three techniques for reasoning and analyzing concurrent programs running under WMMs. The first one is a sound and complete analysis technique for finite-state programs running under the TSO semantics (Paper II). This technique is based on a novel and equivalent semantics for TSO, called Dual TSO semantics, and on the use of well-structured transition framework. The second technique is an under-approximation technique that can be used to detect bugs under the POWER semantics (Paper III). This technique is based on bounding the number of contexts in an explored execution where, in each context, there is only one active process. The third technique is also an under-approximation technique based on systematic testing (a.k.a. stateless model checking). This approach has been used to develop an optimal and efficient systematic testing approach for concurrent programs running under the Release-Acquire semantics (Paper IV).

    The thesis also considers the problem of effectively finding a minimal set of fences that guarantees the correctness of a concurrent program running under WMMs (Paper I). A fence (a.k.a. barrier) is an operation that can be inserted in the program to prohibit certain reorderings between operations issued before and after the fence. Since fences are expensive, it is crucial to automatically find a minimal set of fences to ensure the program correctness. This thesis presents a method for automatic fence insertion in programs running under the TSO semantics that offers the best-known trade-off between the efficiency and optimality of the algorithm. The technique is based on a novel notion of correctness, called Persistence, that compares the behaviors of a program running under WMMs to that running under the SC semantics.

    List of papers
    1. The Best of Both Worlds: Trading efficiency and optimality in fence insertion for TSO
    Open this publication in new window or tab >>The Best of Both Worlds: Trading efficiency and optimality in fence insertion for TSO
    2015 (English)In: Programming Languages and Systems: ESOP 2015, Springer Berlin/Heidelberg, 2015, p. 308-332Conference paper, Published paper (Refereed)
    Abstract [en]

    We present a method for automatic fence insertion in concurrent programs running under weak memory models that provides the best known trade-off between efficiency and optimality. On the one hand, the method can efficiently handle complex aspects of program behaviors such as unbounded buffers and large numbers of processes. On the other hand, it is able to find small sets of fences needed for ensuring correctness of the program. To this end, we propose a novel notion of correctness, called persistence, that compares the behavior of the program under the weak memory semantics with that under the classical interleaving (SC) semantics. We instantiate our framework for the Total Store Ordering (TSO) memory model, and give an algorithm that reduces the fence insertion problem under TSO to the reachability problem for programs running under SC. Furthermore, we provide an abstraction scheme that substantially increases scalability to large numbers of processes. Based on our method, we have implemented a tool and run it successfully on a wide range benchmarks.

    Place, publisher, year, edition, pages
    Springer Berlin/Heidelberg, 2015
    Series
    Lecture Notes in Computer Science, ISSN 0302-9743 ; 9032
    Keywords
    weak memory, correctness, verification, TSO, concurrent program
    National Category
    Computer Sciences
    Research subject
    Computer Science
    Identifiers
    urn:nbn:se:uu:diva-253645 (URN)10.1007/978-3-662-46669-8_13 (DOI)000361751400013 ()978-3-662-46668-1 (ISBN)
    Conference
    24th European Symposium on Programming, ESOP 2015, April 11–18, London, UK
    Projects
    UPMARC
    Available from: 2015-05-29 Created: 2015-05-29 Last updated: 2018-11-21
    2. A load-buffer semantics for total store ordering
    Open this publication in new window or tab >>A load-buffer semantics for total store ordering
    2018 (English)In: Logical Methods in Computer Science, ISSN 1860-5974, E-ISSN 1860-5974, Vol. 14, no 1, article id 9Article in journal (Refereed) Published
    Abstract [en]

    We address the problem of verifying safety properties of concurrent programs running over the Total Store Order (TSO) memory model. Known decision procedures for this model are based on complex encodings of store buffers as lossy channels. These procedures assume that the number of processes is fixed. However, it is important in general to prove the correctness of a system/algorithm in a parametric way with an arbitrarily large number of processes. 

    In this paper, we introduce an alternative (yet equivalent) semantics to the classical one for the TSO semantics that is more amenable to efficient algorithmic verification and for the extension to parametric verification. For that, we adopt a dual view where load buffers are used instead of store buffers. The flow of information is now from the memory to load buffers. We show that this new semantics allows (1) to simplify drastically the safety analysis under TSO, (2) to obtain a spectacular gain in efficiency and scalability compared to existing procedures, and (3) to extend easily the decision procedure to the parametric case, which allows obtaining a new decidability result, and more importantly, a verification algorithm that is more general and more efficient in practice than the one for bounded instances.

    Keywords
    Verification, TSO, concurrent program, safety property, well-structured transition system
    National Category
    Computer Sciences
    Research subject
    Computer Science
    Identifiers
    urn:nbn:se:uu:diva-337278 (URN)000426512000008 ()
    Projects
    UPMARC
    Available from: 2018-01-23 Created: 2017-12-21 Last updated: 2018-11-21
    3. Context-bounded analysis for POWER
    Open this publication in new window or tab >>Context-bounded analysis for POWER
    2017 (English)In: Tools and Algorithms for the Construction and Analysis of Systems: Part II, Springer, 2017, p. 56-74Conference paper, Published paper (Refereed)
    Abstract [en]

    We propose an under-approximate reachability analysis algorithm for programs running under the POWER memory model, in the spirit of the work on context-bounded analysis initiated by Qadeer et al. in 2005 for detecting bugs in concurrent programs (supposed to be running under the classical SC model). To that end, we first introduce a new notion of context-bounding that is suitable for reasoning about computations under POWER, which generalizes the one defined by Atig et al. in 2011 for the TSO memory model. Then, we provide a polynomial size reduction of the context-bounded state reachability problem under POWER to the same problem under SC: Given an input concurrent program P, our method produces a concurrent program P' such that, for a fixed number of context switches, running P' under SC yields the same set of reachable states as running P under POWER. The generated program P' contains the same number of processes as P and operates on the same data domain. By leveraging the standard model checker CBMC, we have implemented a prototype tool and applied it on a set of benchmarks, showing the feasibility of our approach.

    Place, publisher, year, edition, pages
    Springer, 2017
    Series
    Lecture Notes in Computer Science, ISSN 0302-9743, E-ISSN 1611-3349 ; 10206
    Keywords
    POWER, weak memory model, under approximation, translation, concurrent program, testing
    National Category
    Computer Systems
    Research subject
    Computer Science
    Identifiers
    urn:nbn:se:uu:diva-314901 (URN)10.1007/978-3-662-54580-5_4 (DOI)000440733400004 ()978-3-662-54579-9 (ISBN)
    Conference
    23rd International Conference on Tools and Algorithms for the Construction and Analysis of Systems (TACAS), 2017, April 22–29, Uppsala, Sweden
    Projects
    UPMARC
    Available from: 2017-03-31 Created: 2017-02-07 Last updated: 2018-11-21Bibliographically approved
    4. Optimal Stateless Model Checking under the Release-Acquire Semantics
    Open this publication in new window or tab >>Optimal Stateless Model Checking under the Release-Acquire Semantics
    2018 (English)In: SPLASH OOPSLA 2018, Boston, Nov 4-9, 2018, ACM Digital Library, 2018Conference paper, Published paper (Refereed)
    Abstract [en]

    We present a framework for efficient application of stateless model checking (SMC) to concurrent programs running under the Release-Acquire (RA) fragment of the C/C++11 memory model. Our approach is based on exploring the possible program orders, which define the order in which instructions of a thread are executed, and read-from relations, which define how reads obtain their values from writes. This is in contrast to previous approaches, which in addition explore the possible coherence orders, i.e., orderings between conflicting writes. Since unexpected test results such as program crashes or assertion violations depend only on the read-from relation, we avoid a potentially large source of redundancy. Our framework is based on a novel technique for determining whether a particular read-from relation is feasible under the RA semantics. We define an SMC algorithm which is provably optimal in the sense that it explores each program order and read-from relation exactly once. This optimality result is strictly stronger than previous analogous optimality results, which also take coherence order into account. We have implemented our framework in the tool Tracer. Experiments show that Tracer can be significantly faster than state-of-the-art tools that can handle the RA semantics.

    Place, publisher, year, edition, pages
    ACM Digital Library, 2018
    Keywords
    Software model checking, C/C++11, Release-Acquire, Concurrent program
    National Category
    Computer Systems
    Research subject
    Computer Science
    Identifiers
    urn:nbn:se:uu:diva-358241 (URN)
    Conference
    SPLASH OOPSLA 2018
    Projects
    UPMARC
    Available from: 2018-08-26 Created: 2018-08-26 Last updated: 2019-01-09Bibliographically approved
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  • 274.
    Ngo, Tuan-Phong
    et al.
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
    Abdulla, Parosh
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
    Jonsson, Bengt
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology.
    Atig, Mohamed Faouzi
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
    Optimal Stateless Model Checking under the Release-Acquire Semantics2018In: SPLASH OOPSLA 2018, Boston, Nov 4-9, 2018, ACM Digital Library, 2018Conference paper (Refereed)
    Abstract [en]

    We present a framework for efficient application of stateless model checking (SMC) to concurrent programs running under the Release-Acquire (RA) fragment of the C/C++11 memory model. Our approach is based on exploring the possible program orders, which define the order in which instructions of a thread are executed, and read-from relations, which define how reads obtain their values from writes. This is in contrast to previous approaches, which in addition explore the possible coherence orders, i.e., orderings between conflicting writes. Since unexpected test results such as program crashes or assertion violations depend only on the read-from relation, we avoid a potentially large source of redundancy. Our framework is based on a novel technique for determining whether a particular read-from relation is feasible under the RA semantics. We define an SMC algorithm which is provably optimal in the sense that it explores each program order and read-from relation exactly once. This optimality result is strictly stronger than previous analogous optimality results, which also take coherence order into account. We have implemented our framework in the tool Tracer. Experiments show that Tracer can be significantly faster than state-of-the-art tools that can handle the RA semantics.

  • 275.
    Nikoleris, Nikos
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Division of Computer Systems. Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems. Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication.
    Efficient Memory Modeling During Simulation and Native Execution2019Doctoral thesis, comprehensive summary (Other academic)
    Abstract [en]

    Application performance on computer processors depends on a number of complex architectural and microarchitectural design decisions. Consequently, computer architects rely on performance modeling to improve future processors without building prototypes. This thesis focuses on performance modeling and proposes methods that quantify the impact of the memory system on application performance.

    Detailed architectural simulation, a common approach to performance modeling, can be five orders of magnitude slower than execution on the actual processor. At this rate, simulating realistic workloads requires years of CPU time. Prior research uses sampling to speed up simulation. Using sampled simulation, only a number of small but representative portions of the workload are evaluated in detail. To fully exploit the speed potential of sampled simulation, the simulation method has to efficiently reconstruct the architectural and microarchitectural state prior to the simulation samples. Practical approaches to sampled simulation use either functional simulation at the expense of performance or checkpoints at the expense of flexibility. This thesis proposes three approaches that use statistical cache modeling to efficiently address the problem of cache warm up and speed up sampled simulation, without compromising flexibility. The statistical cache model uses sparse memory reuse information obtained with native techniques to model the performance of the cache. The proposed sampled simulation framework evaluates workloads 150 times faster than approaches that use functional simulation to warm up the cache.

    Other approaches to performance modeling use analytical models based on data obtained from execution on native hardware. These native techniques allow for better understanding of the performance bottlenecks on existing hardware. Efficient resource utilization in modern multicore processors is necessary to exploit their peak performance. This thesis proposes native methods that characterize shared resource utilization in modern multicores. These methods quantify the impact of cache sharing and off-chip memory sharing on overall application performance. Additionally, they can quantify scalability bottlenecks for data-parallel, symmetric workloads.

    List of papers
    1. Extending statistical cache models to support detailed pipeline simulators
    Open this publication in new window or tab >>Extending statistical cache models to support detailed pipeline simulators
    2014 (English)In: 2014 IEEE International Symposium On Performance Analysis Of Systems And Software (Ispass), IEEE Computer Society, 2014, p. 86-95Conference paper, Published paper (Refereed)
    Abstract [en]

    Simulators are widely used in computer architecture research. While detailed cycle-accurate simulations provide useful insights, studies using modern workloads typically require days or weeks. Evaluating many design points, only exacerbates the simulation overhead. Recent works propose methods with good accuracy that reduce the simulated overhead either by sampling the execution (e.g., SMARTS and SimPoint) or by using fast analytical models of the simulated designs (e.g., Interval Simulation). While these techniques reduce significantly the simulation overhead, modeling processor components with large state, such as the last-level cache, requires costly simulation to warm them up. Statistical simulation methods, such as SMARTS, report that the warm-up overhead accounts for 99% of the simulation overhead, while only 1% of the time is spent simulating the target design. This paper proposes WarmSim, a method that eliminates the need to warm up the cache. WarmSim builds on top of a statistical cache modeling technique and extends it to model accurately not only the miss ratio but also the outcome of every cache request. WarmSim uses as input, an application's memory reuse information which is hardware independent. Therefore, different cache configurations can be simulated using the same input data. We demonstrate that this approach can be used to estimate the CPI of the SPEC CPU2006 benchmarks with an average error of 1.77%, reducing the overhead compared to a simulation with a 10M instruction warm-up by a factor of 50x.

    Place, publisher, year, edition, pages
    IEEE Computer Society, 2014
    Series
    IEEE International Symposium on Performance Analysis of Systems and Software-ISPASS
    National Category
    Computer Sciences
    Identifiers
    urn:nbn:se:uu:diva-224221 (URN)10.1109/ISPASS.2014.6844464 (DOI)000364102000010 ()978-1-4799-3604-5 (ISBN)
    Conference
    ISPASS 2014, March 23-25, Monterey, CA
    Projects
    UPMARC
    Available from: 2014-05-06 Created: 2014-05-06 Last updated: 2018-12-14Bibliographically approved
    2. CoolSim: Statistical Techniques to Replace Cache Warming with Efficient, Virtualized Profiling
    Open this publication in new window or tab >>CoolSim: Statistical Techniques to Replace Cache Warming with Efficient, Virtualized Profiling
    2016 (English)In: Proceedings Of 2016 International Conference On Embedded Computer Systems: Architectures, Modeling And Simulation (Samos) / [ed] Najjar, W Gerstlauer, A, IEEE , 2016, p. 106-115Conference paper, Published paper (Refereed)
    Abstract [en]

    Simulation is an important part of the evaluation of next-generation computing systems. Detailed, cycle-accurate simulation, however, can be very slow when evaluating realistic workloads on modern microarchitectures. Sampled simulation (e.g., SMARTS and SimPoint) improves simulation performance by an order of magnitude or more through the reduction of large workloads into a small but representative sample. Additionally, the execution state just prior to a simulation sample can be stored into checkpoints, allowing for fast restoration and evaluation. Unfortunately, changes in software, architecture or fundamental pieces of the microarchitecture (e.g., hardware-software co-design) require checkpoint regeneration. The end result for co-design degenerates to creating checkpoints for each modification, a task checkpointing was designed to eliminate. Therefore, a solution is needed that allows for fast and accurate simulation, without the need for checkpoints. Virtualized fast-forwarding (VFF), an alternative to using checkpoints, allows for execution at near-native speed between simulation points. Warming the micro-architectural state prior to each simulation point, however, requires functional simulation, a costly operation for large caches (e.g., 8 M B). Simulating future systems with caches of many MBs can require warming of billions of instructions, dominating simulation time. This paper proposes CoolSim, an efficient simulation framework that eliminates cache warming. CoolSim uses VFF to advance between simulation points collecting at the same time sparse memory reuse information (MRI). The MRI is collected more than an order of magnitude faster than functional simulation. At the simulation point, detailed simulation with a statistical cache model is used to evaluate the design. The previously acquired MRI is used to estimate whether each memory request hits in the cache. The MRI is an architecturally independent metric and a single profile can be used in simulations of any size cache. We describe a prototype implementation of CoolSim based on KVM and gem5 running 19 x faster than the state-of-the-art sampled simulation, while it estimates the CPI of the SPEC CPU2006 benchmarks with 3.62% error on average, across a wide range of cache sizes.

    Place, publisher, year, edition, pages
    IEEE, 2016
    National Category
    Computer Sciences
    Identifiers
    urn:nbn:se:uu:diva-322061 (URN)000399143000015 ()9781509030767 (ISBN)
    Conference
    International Conference on Embedded Computer Systems - Architectures, Modeling and Simulation (SAMOS), JUL 17-21, 2016, Samos, GREECE
    Funder
    Swedish Foundation for Strategic Research EU, FP7, Seventh Framework Programme, 610490
    Available from: 2017-05-16 Created: 2017-05-16 Last updated: 2018-12-14Bibliographically approved
    3. Delorean: Virtualized Directed Profiling for Cache Modeling in Sampled Simulation
    Open this publication in new window or tab >>Delorean: Virtualized Directed Profiling for Cache Modeling in Sampled Simulation
    2018 (English)Report (Other academic)
    Abstract [en]

    Current practice for accurate and efficient simulation (e.g., SMARTS and Simpoint) makes use of sampling to significantly reduce the time needed to evaluate new research ideas. By evaluating a small but representative portion of the original application, sampling can allow for both fast and accurate performance analysis. However, as cache sizes of modern architectures grow, simulation time is dominated by warming microarchitectural state and not by detailed simulation, reducing overall simulation efficiency. While checkpoints can significantly reduce cache warming, improving efficiency, they limit the flexibility of the system under evaluation, requiring new checkpoints for software updates (such as changes to the compiler and compiler flags) and many types of hardware modifications. An ideal solution would allow for accurate cache modeling for each simulation run without the need to generate rigid checkpointing data a priori.

    Enabling this new direction for fast and flexible simulation requires a combination of (1) a methodology that allows for hardware and software flexibility and (2) the ability to quickly and accurately model arbitrarily-sized caches. Current approaches that rely on checkpointing or statistical cache modeling require rigid, up-front state to be collected which needs to be amortized over a large number of simulation runs. These earlier methodologies are insufficient for our goals for improved flexibility. In contrast, our proposed methodology, Delorean, outlines a unique solution to this problem. The Delorean simulation methodology enables both flexibility and accuracy by quickly generating a targeted cache model for the next detailed region on the fly without the need for up-front simulation or modeling. More specifically, we propose a new, more accurate statistical cache modeling method that takes advantage of hardware virtualization to precisely determine the memory regions accessed and to minimize the time needed for data collection while maintaining accuracy.

    Delorean uses a multi-pass approach to understand the memory regions accessed by the next, upcoming detailed region. Our methodology collects the entire set of key memory accesses and, through fast virtualization techniques, progressively scans larger, earlier regions to learn more about these key accesses in an efficient way. Using these techniques, we demonstrate that Delorean allows for the fast evaluation of systems and their software though the generation of accurate cache models on the fly. Delorean outperforms previous proposals by an order of magnitude, with a simulation speed of 150 MIPS and a similar average CPI error (below 4%).

    Publisher
    p. 12
    Series
    Technical report / Department of Information Technology, Uppsala University, ISSN 1404-3203
    National Category
    Computer Systems
    Research subject
    Computer Science
    Identifiers
    urn:nbn:se:uu:diva-369320 (URN)
    Available from: 2018-12-12 Created: 2018-12-12 Last updated: 2019-01-08Bibliographically approved
    4. Cache Pirating: Measuring the Curse of the Shared Cache
    Open this publication in new window or tab >>Cache Pirating: Measuring the Curse of the Shared Cache
    2011 (English)In: Proc. 40th International Conference on Parallel Processing, IEEE Computer Society, 2011, p. 165-175Conference paper, Published paper (Refereed)
    Place, publisher, year, edition, pages
    IEEE Computer Society, 2011
    National Category
    Computer Engineering
    Identifiers
    urn:nbn:se:uu:diva-181254 (URN)10.1109/ICPP.2011.15 (DOI)978-1-4577-1336-1 (ISBN)
    Conference
    ICPP 2011
    Projects
    UPMARCCoDeR-MP
    Available from: 2011-10-17 Created: 2012-09-20 Last updated: 2018-12-14Bibliographically approved
    5. Bandwidth Bandit: Quantitative Characterization of Memory Contention
    Open this publication in new window or tab >>Bandwidth Bandit: Quantitative Characterization of Memory Contention
    2013 (English)In: Proc. 11th International Symposium on Code Generation and Optimization: CGO 2013, IEEE Computer Society, 2013, p. 99-108Conference paper, Published paper (Refereed)
    Abstract [en]

    On multicore processors, co-executing applications compete for shared resources, such as cache capacity and memory bandwidth. This leads to suboptimal resource allocation and can cause substantial performance loss, which makes it important to effectively manage these shared resources. This, however, requires insights into how the applications are impacted by such resource sharing. While there are several methods to analyze the performance impact of cache contention, less attention has been paid to general, quantitative methods for analyzing the impact of contention for memory bandwidth. To this end we introduce the Bandwidth Bandit, a general, quantitative, profiling method for analyzing the performance impact of contention for memory bandwidth on multicore machines. The profiling data captured by the Bandwidth Bandit is presented in a bandwidth graph. This graph accurately captures the measured application's performance as a function of its available memory bandwidth, and enables us to determine how much the application suffers when its available bandwidth is reduced. To demonstrate the value of this data, we present a case study in which we use the bandwidth graph to analyze the performance impact of memory contention when co-running multiple instances of single threaded application.

    Place, publisher, year, edition, pages
    IEEE Computer Society, 2013
    Keywords
    bandwidth, memory, caches
    National Category
    Computer Sciences
    Research subject
    Computer Science
    Identifiers
    urn:nbn:se:uu:diva-194101 (URN)10.1109/CGO.2013.6494987 (DOI)000318700200010 ()978-1-4673-5524-7 (ISBN)
    Conference
    CGO 2013, 23-27 February, Shenzhen, China
    Projects
    UPMARC
    Funder
    Swedish Research Council
    Available from: 2013-04-18 Created: 2013-02-08 Last updated: 2018-12-14Bibliographically approved
    6. A software based profiling method for obtaining speedup stacks on commodity multi-cores
    Open this publication in new window or tab >>A software based profiling method for obtaining speedup stacks on commodity multi-cores
    2014 (English)In: 2014 IEEE INTERNATIONAL SYMPOSIUM ON PERFORMANCE ANALYSIS OF SYSTEMS AND SOFTWARE (ISPASS): ISPASS 2014, IEEE Computer Society, 2014, p. 148-157Conference paper, Published paper (Refereed)
    Abstract [en]

    A key goodness metric of multi-threaded programs is how their execution times scale when increasing the number of threads. However, there are several bottlenecks that can limit the scalability of a multi-threaded program, e.g., contention for shared cache capacity and off-chip memory bandwidth; and synchronization overheads. In order to improve the scalability of a multi-threaded program, it is vital to be able to quantify how the program is impacted by these scalability bottlenecks. We present a software profiling method for obtaining speedup stacks. A speedup stack reports how much each scalability bottleneck limits the scalability of a multi-threaded program. It thereby quantifies how much its scalability can be improved by eliminating a given bottleneck. A software developer can use this information to determine what optimizations are most likely to improve scalability, while a computer architect can use it to analyze the resource demands of emerging workloads. The proposed method profiles the program on real commodity multi-cores (i.e., no simulations required) using existing performance counters. Consequently, the obtained speedup stacks accurately account for all idiosyncrasies of the machine on which the program is profiled. While the main contribution of this paper is the profiling method to obtain speedup stacks, we present several examples of how speedup stacks can be used to analyze the resource requirements of multi-threaded programs. Furthermore, we discuss how their scalability can be improved by both software developers and computer architects.

    Place, publisher, year, edition, pages
    IEEE Computer Society, 2014
    Series
    IEEE International Symposium on Performance Analysis of Systems and Software-ISPASS
    National Category
    Computer Sciences
    Identifiers
    urn:nbn:se:uu:diva-224230 (URN)10.1109/ISPASS.2014.6844479 (DOI)000364102000025 ()978-1-4799-3604-5 (ISBN)
    Conference
    ISPASS 2014, March 23-25, Monterey, CA
    Projects
    UPMARC
    Available from: 2014-05-06 Created: 2014-05-06 Last updated: 2018-12-14Bibliographically approved
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  • 276.
    Nikoleris, Nikos
    et al.
    Arm Res, Cambridge, England.
    Eeckhout, Lieven
    Univ Ghent, Ghent, Belgium.
    Hagersten, Erik
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
    Carlson, Trevor E.
    Natl Univ Singapore, Singapore, Singapore.
    Directed Statistical Warming through Time Traveling2019In: MICRO'52: The 52nd Annual IEEE/ACM International Symposium On Microarchitecture, 2019, p. 1037-1049Conference paper (Refereed)
    Abstract [en]

    Improving the speed of computer architecture evaluation is of paramount importance to shorten the time-to-market when developing new platforms. Sampling is a widely used methodology to speed up workload analysis and performance evaluation by extrapolating from a set of representative detailed regions. Installing an accurate cache state for each detailed region is critical to achieving high accuracy. Prior work requires either huge amounts of storage (checkpoint-based warming), an excessive number of memory accesses to warm up the cache (functional warming), or the collection of a large number of reuse distances (randomized statistical warming) to accurately predict cache warm-up effects. This work proposes DeLorean, a novel statistical warming and sampling methodology that builds upon two key contributions: directed statistical warming and time traveling. Instead of collecting a large number of randomly selected reuse distances as in randomized statistical warming, directed statistical warming collects a select number of key reuse distances, i.e., the most recent reuse distance for each unique memory location referenced in the detailed region. Time traveling leverages virtualized fast-forwarding to quickly 'look into the future' - to determine the key cachelines - and then 'go back in time' - to collect the reuse distances for those key cachelines at near-native hardware speed through virtualized directed profiling. Directed statistical warming reduces the number of warm-up references by 30x compared to randomized statistical warming. Time traveling translates this reduction into a 5.7x simulation speedup. In addition to improving simulation speed, DeLorean reduces the prediction error from around 9% to around 3% on average. We further demonstrate how to amortize warm-up cost across multiple parallel simulations in design space exploration studies. Implementing DeLorean in gem5 enables detailed cycle-accurate simulation at a speed of 126 MIPS.

  • 277.
    Nikoleris, Nikos
    et al.
    Arm Research, Cambridge UK.
    Hagersten, Erik
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication. Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
    Carlson, Trevor E.
    Department of Computer Science, National University of Singapore.
    Delorean: Virtualized Directed Profiling for Cache Modeling in Sampled Simulation2018Report (Other academic)
    Abstract [en]

    Current practice for accurate and efficient simulation (e.g., SMARTS and Simpoint) makes use of sampling to significantly reduce the time needed to evaluate new research ideas. By evaluating a small but representative portion of the original application, sampling can allow for both fast and accurate performance analysis. However, as cache sizes of modern architectures grow, simulation time is dominated by warming microarchitectural state and not by detailed simulation, reducing overall simulation efficiency. While checkpoints can significantly reduce cache warming, improving efficiency, they limit the flexibility of the system under evaluation, requiring new checkpoints for software updates (such as changes to the compiler and compiler flags) and many types of hardware modifications. An ideal solution would allow for accurate cache modeling for each simulation run without the need to generate rigid checkpointing data a priori.

    Enabling this new direction for fast and flexible simulation requires a combination of (1) a methodology that allows for hardware and software flexibility and (2) the ability to quickly and accurately model arbitrarily-sized caches. Current approaches that rely on checkpointing or statistical cache modeling require rigid, up-front state to be collected which needs to be amortized over a large number of simulation runs. These earlier methodologies are insufficient for our goals for improved flexibility. In contrast, our proposed methodology, Delorean, outlines a unique solution to this problem. The Delorean simulation methodology enables both flexibility and accuracy by quickly generating a targeted cache model for the next detailed region on the fly without the need for up-front simulation or modeling. More specifically, we propose a new, more accurate statistical cache modeling method that takes advantage of hardware virtualization to precisely determine the memory regions accessed and to minimize the time needed for data collection while maintaining accuracy.

    Delorean uses a multi-pass approach to understand the memory regions accessed by the next, upcoming detailed region. Our methodology collects the entire set of key memory accesses and, through fast virtualization techniques, progressively scans larger, earlier regions to learn more about these key accesses in an efficient way. Using these techniques, we demonstrate that Delorean allows for the fast evaluation of systems and their software though the generation of accurate cache models on the fly. Delorean outperforms previous proposals by an order of magnitude, with a simulation speed of 150 MIPS and a similar average CPI error (below 4%).

    Download full text (pdf)
    fulltext
  • 278.
    Nikoleris, Nikos
    et al.
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
    Sandberg, Andreas
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
    Hagersten, Erik
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
    Carlson, Trevor E.
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
    CoolSim: Eliminating Traditional Cache Warming with Fast, Virtualized Profiling2016In: 2016 IEEE International Symposium On Performance Analysis Of Systems And Software ISPASS 2016, 2016, p. 149-150Conference paper (Refereed)
    Abstract [en]

    Sampling (e.g., SMARTS and SimPoint) improves simulation performance by an order of magnitude or more through the reduction of large workloads into a small but representative sample. Virtualized fast-forwarding (e.g., FSA) speeds up simulation further by advancing execution at near-native speed between simulation points, making cache warming the critical limiting factor for simulation performance. CoolSim is an efficient simulation framework that eliminates cache warming. It collects sparse memory reuse information (MRI) while advancing between simulation points using virtualized fast-forwarding. During detailed simulation, a statistical cache model uses the previously acquired MRI to estimate the performance of the caches. CoolSim builds upon KVM and gem5 and runs 19x faster than the state-of-the-art sampled simulation. It estimates the CPI of the SPEC CPU2006 bench-marks with 3.62% error on average, across a wide range of cache sizes.

  • 279.
    Nordén, Lars-Åke
    et al.
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
    Mannila, Linda
    Linkoping Univ, Dept Comp & Informat Sci, Linkoping, Sweden.
    Pears, Arnold
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
    Development of a self-efficacy scale for digital competences in schools2017In: 2017 IEEE Frontiers in Education Conference (FIE): Proc. 47th ASEE/IEEE Frontiers in Education Conference, IEEE Press, 2017Conference paper (Refereed)
    Abstract [en]

    As computer science enters the school curricula in an increasing number of countries, teachers must prepare to integrate digital competences into their teaching. This integration is a moving target where new methods, tools and applications appear and disappear at such rates that teachers must have confidence to independently and continuously explore what is new, what is relevant and how to plan their pedagogic activities to include digital competences. In this context approaches which can be used to study self-efficacy in digital competences among school teachers are desperately needed. With such a tool in place, we can make a baseline study and then follow teachers over time to measure changes in their self-efficacy, the cause of these changes and learn how to build their digital competence self-efficacy in different ways. The same tool can also be used to measure the self-efficacy in other populations, e.g., students in teacher training programs to ensure that they obtain an adequate self-efficacy in digital competences during their studies. This paper describes the development of a self-efficacy scale in digital competences, based on the DigiComp 2.0 framework definition of digital competence. The tool focuses predominantly on digital competences relevant for teachers in school years K-9.

    Download full text (pdf)
    fulltext
  • 280.
    Nylén, Aletta
    et al.
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computing Science.
    Cajander, Åsa
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computerized Image Analysis and Human-Computer Interaction.
    Daniels, Mats
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
    Pears, Arnold
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
    McDermott, Roger
    Why are we here?: Student perspectives on the goal of STEM higher education2017In: Proc. 47th ASEE/IEEE Frontiers in Education Conference, Piscataway, NJ: IEEE Press, 2017Conference paper (Refereed)
  • 281.
    Nylén, Aletta
    et al.
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computing Science.
    Daniels, Mats
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
    Isomöttönen, Ville
    McDermott, Roger
    Open-ended projects opened up – aspects of openness2017In: Proc. 47th ASEE/IEEE Frontiers in Education Conference, Piscataway, NJ: IEEE Press, 2017Conference paper (Refereed)
  • 282.
    Nylén, Aletta
    et al.
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computing Science.
    Daniels, Mats
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
    Pears, Arnold
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
    Cajander, Åsa
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computerized Image Analysis and Human-Computer Interaction.
    McDermott, Roger
    Robert GordoSchool of Computer Science and Digital Media, Robert Gordon University, Aberdeen, UK.
    Isomöttönen, Ville
    Faculty of Information Technology, University of Jyväskylä, Finland.
    Why are we here?: The educational value model (EVM) as a framework to investigate the role of students’ professional identity development2018In: 2018 IEEE Frontiers in Education Conference (FIE), Piscataway, NJ: IEEE, 2018Conference paper (Refereed)
    Abstract [en]

    Education can be seen as a preparation for a future profession, where some educational programs very clearly prepare their students for a certain profession, e.g. plumber, nurse and architect. The possible professions for students following education programs in computing is quite varied and thus difficult to cater for, but to educate towards a professional life is still a stated goal in most higher education settings. We argue that this goal is typically not even closely reached and provide an analysis indicating factors explaining this situation. The analysis is based on the concept of professional identity. In earlier work [1] a framework with which to reason about student interactions with the regulatory structure of higher education and teachers was developed. In that paper we developed a compound model which not only relates these players to one another, but also provides approaches to reasoning about misalignments which arise when students and teachers approach their shared learning context from different perspectives. This framework is in this paper applied to address different aspects of professional identity with the intent of bringing forth deeper insights into challenges with educating towards professions. This issue is highly complex and the framework provides a structure that is beneficial for analysing different aspects in a more holistic manner.

  • 283.
    Nylén, Aletta
    et al.
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computing Science.
    Thota, Neena
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
    Eckerdal, Anna
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Division of Scientific Computing. Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computational Science.
    Kinnunen, Päivi
    Butler, Matthew
    Morgan, Michael
    Multidimensional analysis of creative coding MOOC forums: a methodological discussion2015In: Proc. 15th International Conference on Computing Education Research: Koli Calling, New York: ACM Press, 2015, p. 137-141Conference paper (Refereed)
  • 284.
    Pan, Xiaoyue
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Division of Computer Systems. Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
    Performance Modeling of Multi-core Systems: Caches and Locks2016Doctoral thesis, comprehensive summary (Other academic)
    Abstract [en]

    Performance is an important aspect of computer systems since it directly affects user experience. One way to analyze and predict performance is via performance modeling. In recent years, multi-core systems have made processors more powerful while keeping power consumption relatively low. However the complicated design of these systems makes it difficult to analyze performance. This thesis presents performance modeling techniques for cache performance and synchronization cost on multi-core systems.

    A cache can be designed in many ways with different configuration parameters including cache size, associativity and replacement policy. Understanding cache performance under different configurations is useful to explore the design choices. We propose a general modeling framework for estimating the cache miss ratio under different cache configurations, based on the reuse distance distribution. On multi-core systems, each core usually has a private cache. Keeping shared data in private caches coherent has an extra cost. We propose three models to estimate this cost, based on information that can be gathered when running the program on a single core.

    Locks are widely used as a synchronization primitive in multi-threaded programs on multi-core systems. While they are often necessary for protecting shared data, they also introduce lock contention, which causes performance issues. We present a model to predict how much contention a lock has on multi-core systems, based on information obtainable from profiling a run on a single core. If lock contention is shown to be a performance bottleneck, one of the ways to mitigate it is to use another lock implementation. However, it is costly to investigate if adopting another lock implementation would reduce lock contention since it requires reimplementation and measurement. We present a model for forecasting lock contention with another lock implementation without replacing the current lock implementation.

    List of papers
    1. A Modeling Framework for Reuse Distance-based Estimation of Cache Performance
    Open this publication in new window or tab >>A Modeling Framework for Reuse Distance-based Estimation of Cache Performance
    2015 (English)In: Performance Analysis of Systems and Software (ISPASS), 2015 IEEE International Symposium on, IEEE, 2015, p. 62-71Conference paper, Published paper (Refereed)
    Abstract [en]

    We develop an analytical modeling framework for efficient prediction of cache miss ratios based on reuse distance distributions. The only input needed for our predictions is the reuse distance distribution of a program execution: previous work has shown that they can be obtained with very small overhead by sampling from native executions. This should be contrasted with previous approaches that base predictions on stack distance distributions, whose collection need significantly larger overhead or additional hardware support. The predictions are based on a uniform modeling framework which can be specialized for a variety of cache replacement policies, including Random, LRU, PLRU, and MRU (aka. bit-PLRU), and for arbitrary values of cache size and cache associativity. We evaluate our modeling framework with the SPEC CPU 2006 benchmark suite over a set of cache configurations with varying cache size, associativity and replacement policy. The introduced inaccuracies were generally below 1% for the model of the policy, and additionally around 2% when set-local reuse distances must be estimated from global reuse distance distributions. The inaccuracy introduced by sampling is significantly smaller.

    Place, publisher, year, edition, pages
    IEEE: , 2015
    National Category
    Computer Systems
    Research subject
    Computer Science
    Identifiers
    urn:nbn:se:uu:diva-260767 (URN)10.1109/ISPASS.2015.7095785 (DOI)000380554200007 ()9781479919574 (ISBN)
    External cooperation:
    Conference
    2015 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS),
    Projects
    UPMARC
    Available from: 2015-08-24 Created: 2015-08-24 Last updated: 2016-09-15Bibliographically approved
    2. Modeling cache coherence misses on multicores
    Open this publication in new window or tab >>Modeling cache coherence misses on multicores
    2014 (English)In: 2014 IEEE INTERNATIONAL SYMPOSIUM ON PERFORMANCE ANALYSIS OF SYSTEMS AND SOFTWARE (ISPASS), IEEE, 2014, p. 96-105Conference paper, Published paper (Refereed)
    Abstract [en]

    While maintaining the coherency of private caches, invalidation-based cache coherence protocols introduce cache coherence misses. We address the problem of predicting the number of cache coherence misses in the private cache of a parallel application when running on a multicore system with an invalidation-based cache coherence protocol. We propose three new performance models (uniform, phased and symmetric) for estimating the number of coherence misses from information about inter-core data sharing patterns and the individual core's data reuse patterns. The inputs to the uniform and phased models are the write frequency and reuse distance distribution of shared data from different cores. This input can be obtained either from profiling the target application on a single core or by analyzing the data access pattern statically, and does not need a detailed simulation of the pattern of interleaving accesses to shared data. The output of the models is an estimated number of coherence misses of the target application. The output can be combined with the number of other kinds of misses to estimate the total number of misses in each core's private cache. This output can also be used to guide program optimization to improve cache performance. We evaluate our models with a set of benchmarks from the PARSEC benchmark suite on real hardware.

    Place, publisher, year, edition, pages
    IEEE: , 2014
    Series
    IEEE International Symposium on Performance Analysis of Systems and Software-ISPASS
    National Category
    Computer Systems
    Research subject
    Computer Science
    Identifiers
    urn:nbn:se:uu:diva-238139 (URN)10.1109/ISPASS.2014.6844465 (DOI)000364102000011 ()978-1-4799-3604-5 (ISBN)
    Conference
    2014 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), Monterey, CA
    Projects
    UPMARC
    Available from: 2014-12-09 Created: 2014-12-09 Last updated: 2016-02-22Bibliographically approved
    3. Predicting the Cost of Lock Contention in Parallel Applications on Multicores using Analytic Modeling
    Open this publication in new window or tab >>Predicting the Cost of Lock Contention in Parallel Applications on Multicores using Analytic Modeling
    2012 (English)In: Proc. 5th Swedish Workshop on Multi-Core Computing, 2012Conference paper, Published paper (Other academic)
    National Category
    Computer Sciences
    Identifiers
    urn:nbn:se:uu:diva-270130 (URN)
    Conference
    MCC12
    Projects
    UPMARC
    Available from: 2012-11-23 Created: 2015-12-21 Last updated: 2018-01-10Bibliographically approved
    4. Forecasting Lock Contention Before Adopting Another Lock Algorithm
    Open this publication in new window or tab >>Forecasting Lock Contention Before Adopting Another Lock Algorithm
    2015 (English)Report (Other academic)
    National Category
    Computer Sciences
    Identifiers
    urn:nbn:se:uu:diva-270716 (URN)
    Available from: 2016-01-03 Created: 2016-01-03 Last updated: 2018-01-10Bibliographically approved
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    presentationsbild
  • 285.
    Pan, Xiaoyue
    et al.
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
    Jonsson, Bengt
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
    A Modeling Framework for Reuse Distance-based Estimation of Cache Performance2015In: Performance Analysis of Systems and Software (ISPASS), 2015 IEEE International Symposium on, IEEE, 2015, p. 62-71Conference paper (Refereed)
    Abstract [en]

    We develop an analytical modeling framework for efficient prediction of cache miss ratios based on reuse distance distributions. The only input needed for our predictions is the reuse distance distribution of a program execution: previous work has shown that they can be obtained with very small overhead by sampling from native executions. This should be contrasted with previous approaches that base predictions on stack distance distributions, whose collection need significantly larger overhead or additional hardware support. The predictions are based on a uniform modeling framework which can be specialized for a variety of cache replacement policies, including Random, LRU, PLRU, and MRU (aka. bit-PLRU), and for arbitrary values of cache size and cache associativity. We evaluate our modeling framework with the SPEC CPU 2006 benchmark suite over a set of cache configurations with varying cache size, associativity and replacement policy. The introduced inaccuracies were generally below 1% for the model of the policy, and additionally around 2% when set-local reuse distances must be estimated from global reuse distance distributions. The inaccuracy introduced by sampling is significantly smaller.

  • 286.
    Pan, Xiaoyue
    et al.
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
    Klaftenegger, David
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computing Science.
    Jonsson, Bengt
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
    Forecasting Lock Contention Before Adopting Another Lock Algorithm2015Report (Other academic)
    Download full text (pdf)
    fulltext
  • 287.
    Panda, Anmol
    et al.
    BITS Pilani KK Birla Goa Campus, Dept Comp Sci & Informat Syst, Sancoale, Goa, India..
    Rümmer, Philipp
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
    Goveas, Neena
    BITS Pilani KK Birla Goa Campus, Dept Comp Sci & Informat Syst, Sancoale, Goa, India..
    A Comparative Study of GPUVerify and GKLEE2016In: 2016 Fourth International Conference On Parallel, Distributed And Grid Computing (PDGC) / [ed] Kumar, P Singh, AK, IEEE , 2016, p. 112-117Conference paper (Refereed)
    Abstract [en]

    Use of Graphics Processing Unit (CPU) software is increasing due to the need for data intensive operations and availability of GPUs. This has led to a need for effective GPU software verification tools. These tools have to satisfy requirements such as accuracy, reliability and ease of use. In this work, we have considered two such tools: GPUVerify and GKLEE. Our objectives were to learn about the common challenges developers faced in GPU programming, to understand the specific bugs that these two tools report and compare their scope and scalability aspects. We have also considered usability and learnability aspects. In order to test the software, twenty-six benchmarks were selected from open-source applications. These benchmarks were then verified using the tools and the results documented and analysed. The conclusions have been included in the final section.

  • 288.
    Pears, Arnold
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
    Assuring the Quality of Engineering Education2015In: 2015 International Conference on Learning and Teaching in Computing and Engineering, 2015, p. 108-111Conference paper (Refereed)
    Abstract [en]

    Only the foolhardy would question the importance and status that quality assurance holds in the current political climate that prevails for higher education. This paper critiques the culture of higher education quality assurance and accreditation that has emerged over the last twenty years. An underlying trend that influences quality systems for higher education is the focus on process and service. This results in quality systems that focus on documenting educational processes, and which often assume that students are a type of customer, and education a type of service. This paper argues that this educational epistemology oversimplifies the nature and role of higher education. We argue that a more holistic quality evaluation model is needed, including often overlooked aspects of quality such as curriculum, pedagogical aspects of instructional design combined with industrial and educational quality assurance processes that can better meet the needs of practitioners and institutions.

  • 289.
    Pears, Arnold
    et al.
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
    Daniels, Mats
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
    Cajander, Åsa
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computerized Image Analysis and Human-Computer Interaction.
    The Archetype Learning Method: Scaffolding teamwork competences in the engineering classroom2017In: Proc. 47th ASEE/IEEE Frontiers in Education Conference, Piscataway, NJ: IEEE Press, 2017Conference paper (Refereed)
  • 290.
    Pears, Arnold
    et al.
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
    Nylén, Aletta
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computing Science.
    Implications of anonymous assessment2015In: Proc. 45th ASEE/IEEE Frontiers in Education Conference, Piscataway, NJ: IEEE Press, 2015, p. 1404-1408Conference paper (Refereed)
    Abstract [en]

    The role of anonymous assessment in ensuring fair and equitable outcomes for students has been one of the major tenets of educational reform over the last few decades [1]. One of the major goals of these efforts is to reduce the impact of subconscious discriminatory behaviour in assigning grades based on perceptions of ability of gender or minority groups by the examiner. Recently however research has been emerging which challenges the widespread assumptions about the benefits of anonymity drawn from Newstead's work. Contrary results include the work of Dorsey and Colliver, 1995, in medical education, and Batten et al. 2013, who explore the impact of student reputation on assessment. These and many other studies conclude that anonymous assessment resulted in no apparent changes in assessment outcomes. In this paper we explore the implications of anonymity taking examples from educational settings where student anonymity is already an adopted practice. We discuss the positive and negative implications of student anonymity, and identify areas for future research.

  • 291.
    Pears, Arnold
    et al.
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
    Nylén, Aletta
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computing Science.
    Daniels, Mats
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
    A critical analysis of trends in student-centric engineering education and their implications for learning2016In: Proc. 46th ASEE/IEEE Frontiers in Education Conference, Piscataway, NJ: IEEE Press, 2016Conference paper (Refereed)
    Abstract [en]

    Student-centric education has emerged as a dominant aspect of Higher Education policy over the last two decades. Much has been written about the benefits of student active educational approaches, and applied educational research, for instance the meta-study of Hattie, places emphasis on student-centric learning practices that enhance achieved learning outcomes.

    Most existing studies have been evaluations of single courses. In contrast this study focusses on the complete study context of the learner, who typically is in the situation of reading two or three courses simultaneously.

    Our primary goal in this paper is to explore potential challenges as we attempt to scale up active learning to encompass the full curricula. We use a mixture of interview and survey data collected from staff, combined with course schedules and student input to explore some of the potential implications of mandating a student-centric approach over an entire curriculum.

  • 292.
    Perez Penichet, Carlos
    et al.
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication.
    Hermans, Frederik
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication. Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
    Varshney, Ambuj
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication. Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
    Voigt, Thiemo
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication. Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems. SICS Swedish ICT, Stockholm, Sweden.
    Demo: Passive Sensor Tags2016In: Mobicom'16: Proceedings Of The 22Nd Annual International Conference On Mobile Computing And Networking / [ed] ACM, 2016, p. 477-478Conference paper (Refereed)
    Abstract [en]

    The sensing capabilities of an Internet-of-Things (IoT) network are usually fixed at deployment. Adding new sensing modalities is a cumbersome process because it requires altering the deployed hardware. We introduce passive sensor tags that allow to easily and seamlessly add new sensors to existing IoT deployments without requiring hardware modifications or additional energy sources. Passive sensor tags employ backscatter communication to generate transmissions that can be decoded by the radio transceivers present in today's IoT devices. Furthermore, unlike recent works, our approach does not require dedicated infrastructure to generate the unmodulated carrier used for backscatter communication. The demo showcases our prototype of a passive sensor tag collecting sensor data and delivering it to unmodified commodity IoT devices using passive 802.15.4 transmissions.

    Download full text (pdf)
    fulltext
  • 293.
    Peters, Anne-Kathrin
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
    Learning Computing at University: Participation and Identity: A Longitudinal Study2017Doctoral thesis, comprehensive summary (Other academic)
    Abstract [en]

    Computing education has struggled with student engagement and diversity in the student population for a long time. Research in science, technology, engineering, and mathematics (STEM) education suggests that taking a social, long-term perspective on learning is a fruitful approach to resolving some of these persistent challenges.

    A longitudinal study has been conducted, following students from two computing study programmes (CS/IT) over a three-year period. The students reflected on their experiences with CS/IT in a series of interviews. Drawing on social identity theory, the analysis has focused on describing participation in CS/IT, doing, thinking, feeling in relation to CS/IT, as negotiated among different people.

    Phenomenographic analysis yields an outcome space that describes increasingly broad ways in which the students experience participation in CS/IT over the years. Two further outcome spaces provide nuanced insights into experiences that are of increasing relevance as the students advance in their studies; participation as problem solving and problem solving for others. Problem solving defined as solving difficult (technical) problems seems predominate in the learning environment. Problem solving for others brings the user into perspective, but first in the human computer interaction (HCI) course in year three. Students react with scepticism to HCI, excluding HCI from computing, some are students who commenced their studies with broader interests in computing.

    Demonstrating (technical) problem solving competence is the most vital indicator competence in the two study programmes and the students adapt their reflections on who they are as computing students and professionals accordingly. People showing broader interests in computing risk being marginalised. I identify a gap between conceptions of computing as interdisciplinary and important for society and constructions of computing as technical. Closing the gap could improve retention and diversity, and result in graduates that are better prepared to contribute to societal development.

    List of papers
    1. Students' experiences and attitudes towards learning Computer Science
    Open this publication in new window or tab >>Students' experiences and attitudes towards learning Computer Science
    2012 (English)In: Proc. 42nd ASEE/IEEE Frontiers in Education Conference, Piscataway, NJ: IEEE , 2012, p. 88-93Conference paper, Published paper (Refereed)
    Place, publisher, year, edition, pages
    Piscataway, NJ: IEEE, 2012
    National Category
    Computer Sciences Educational Sciences
    Identifiers
    urn:nbn:se:uu:diva-184605 (URN)10.1109/FIE.2012.6462238 (DOI)000356489200033 ()978-1-4673-1353-7 (ISBN)
    Available from: 2012-10-06 Created: 2012-11-09 Last updated: 2018-01-12Bibliographically approved
    2. Engagement in Computer Science and IT — What!: A matter of identity?
    Open this publication in new window or tab >>Engagement in Computer Science and IT — What!: A matter of identity?
    2013 (English)In: Proc. 1st International Conference on Learning and Teaching in Computing and Engineering, Los Alamitos, CA: IEEE Computer Society, 2013, p. 114-121Conference paper, Published paper (Refereed)
    Place, publisher, year, edition, pages
    Los Alamitos, CA: IEEE Computer Society, 2013
    National Category
    Computer Sciences Educational Sciences
    Identifiers
    urn:nbn:se:uu:diva-202686 (URN)10.1109/LaTiCE.2013.42 (DOI)000324484000016 ()978-1-4673-5627-5 (ISBN)
    Conference
    LaTiCE 2013
    Available from: 2013-06-22 Created: 2013-06-25 Last updated: 2018-01-11Bibliographically approved
    3. First year Computer Science and IT students' experience of participation in the discipline
    Open this publication in new window or tab >>First year Computer Science and IT students' experience of participation in the discipline
    2014 (English)In: Proc. 2nd International Conference on Learning and Teaching in Computing and Engineering, Los Alamitos, CA: IEEE Computer Society, 2014, p. 1-8Conference paper, Published paper (Refereed)
    Place, publisher, year, edition, pages
    Los Alamitos, CA: IEEE Computer Society, 2014
    National Category
    Computer Sciences Educational Sciences
    Identifiers
    urn:nbn:se:uu:diva-224653 (URN)10.1109/LaTiCE.2014.9 (DOI)000355978500001 ()978-1-4799-3591-8 (ISBN)
    Conference
    LaTiCE 2014
    Available from: 2014-06-10 Created: 2014-05-16 Last updated: 2018-01-11Bibliographically approved
    4. Second year Computer Science and IT students' experience of participation in the discipline
    Open this publication in new window or tab >>Second year Computer Science and IT students' experience of participation in the discipline
    2015 (English)In: Proc. 15th International Conference on Computing Education Research: Koli Calling, New York: ACM Press, 2015, p. 68-76Conference paper, Published paper (Refereed)
    Place, publisher, year, edition, pages
    New York: ACM Press, 2015
    National Category
    Computer Sciences Educational Sciences
    Identifiers
    urn:nbn:se:uu:diva-269178 (URN)10.1145/2828959.2828962 (DOI)978-1-4503-4020-5 (ISBN)
    Available from: 2015-11-21 Created: 2015-12-14 Last updated: 2018-01-10Bibliographically approved
    5. Students' experience of participation in a discipline: A longitudinal study of computer science and IT engineering students
    Open this publication in new window or tab >>Students' experience of participation in a discipline: A longitudinal study of computer science and IT engineering students
    2018 (English)In: ACM Transactions on Computing Education, ISSN 1946-6226, E-ISSN 1946-6226, Vol. 19, no 1, article id 5Article in journal (Refereed) Published
    National Category
    Computer and Information Sciences Educational Sciences
    Identifiers
    urn:nbn:se:uu:diva-331401 (URN)10.1145/3230011 (DOI)000456615300005 ()
    Available from: 2018-09-28 Created: 2017-10-13 Last updated: 2019-12-06Bibliographically approved
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  • 294.
    Peters, Anne-Kathrin
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
    Participation and learner trajectories in computing education2019In: Bridging Research and Practice in Science Education, Springer, 2019, p. 139-152Chapter in book (Refereed)
  • 295.
    Peters, Anne-Kathrin
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
    Students' experience of participation in a discipline: A longitudinal study of computer science and IT engineering students2018In: ACM Transactions on Computing Education, ISSN 1946-6226, E-ISSN 1946-6226, Vol. 19, no 1, article id 5Article in journal (Refereed)
  • 296.
    Peters, Anne-Kathrin
    et al.
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
    Berglund, Anders
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
    Eckerdal, Anna
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Division of Scientific Computing. Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computational Science.
    Pears, Arnold
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
    Second year Computer Science and IT students' experience of participation in the discipline2015In: Proc. 15th International Conference on Computing Education Research: Koli Calling, New York: ACM Press, 2015, p. 68-76Conference paper (Refereed)
  • 297.
    Peters, Anne-Kathrin
    et al.
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
    Daniels, Mats
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
    Cajander, Åsa
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computerized Image Analysis and Human-Computer Interaction.
    Utilising Diversity for Project Work and Learning: A Study of the Learning Agreement Intervention2019Conference paper (Refereed)
    Abstract [en]

    The learning agreement has great potential as a learning intervention that supports learners to take ownership of their learning and to develop in ways that are meaningful to them. It is useful to educate a diverse student cohort. In a project course as the one investigated in this study, the learning agreement intervention can be beneficial to make use of the different experiences and competencies that a diverse student group brings to the table. In practice however, the learning agreement invention is uncommon in education and not well understood. As it is used in the present study, it is essentially a document in which the students describe competencies that they want to develop, as well as how they will develop and assess those competencies. This study has investigated the learning agreement intervention as it was conducted in an open-ended group project, in particular a workshop to improve the quality and usefulness of the students' learning agreements. Two versions of learning agreements, the one before the workshop and the one after, from 19 students were analysed, as well as semi-structured interview data with the students. We find that many learning agreements are of little use, even after the workshop. A qualitative thematic analysis suggests that the students experience the learning agreement and workshop as useful but that they still struggle with the learning agreement, particularly with describing activities to develop and assess their learning. We derive ideas for how to improve the learning agreement intervention, e.g. by integrating it more with the project work.

  • 298.
    Peters, Anne-Kathrin
    et al.
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
    Hussain, Waqar
    Cajander, Åsa
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computerized Image Analysis and Human-Computer Interaction.
    Clear, Tony
    Daniels, Mats
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
    Preparing the global software engineer2015In: Proc. 10th International Conference on Global Software Engineering, Los Alamitos, CA: IEEE Computer Society, 2015, p. 61-70Conference paper (Refereed)
  • 299.
    Peters, Anne-Kathrin
    et al.
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
    Oden Choi, Judeth
    The making of a computer scientist2018In: XRDS, ISSN 1528-4972, Vol. 25, no 1, p. 7-8Article in journal (Refereed)
  • 300.
    Pinol, Oriol Pinol
    et al.
    Yanzi Networks AB, Stockholm, Sweden..
    Raza, Shahid
    SICS Swedish ICT, Stockholm, Sweden..
    Eriksson, Joakim
    Yanzi Networks AB, Stockholm, Sweden.;SICS Swedish ICT, Stockholm, Sweden..
    Voigt, Thiemo
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems. SICS Swedish ICT, Stockholm, Sweden..
    BSD-based Elliptic Curve Cryptography for the Open Internet of Things2015In: 2015 7Th International Conference On New Technologies, Mobility And Security (NtTMS), 2015Conference paper (Refereed)
    Abstract [en]

    The Internet of Things (IoT) is the interconnection of everyday physical objects with the Internet and their representation in the digital world. Due to the connectivity of physical objects with the untrusted Internet, security has become an important pillar for the success of IoT-based services. Things in the IoT are resource-constrained devices with limited processing and storage capabilities. Often, these things are battery powered and connected through lossy wireless links. Therefore, lightweight and efficient ways of providing secure communication in the IoT are needed. In this context, Elliptic Curve Cryptography (ECC) is considered as a strong candidate to provide security in the IoT while being able to function in constrained environments. In this paper we present a lightweight implementation and evaluation of ECC for the Contiki OS. For fast, secure and cost-effective mass development of IoT-based services by different vendors, it is important that the IoT protocols are implemented and released as open source and open licensed. To the best of our knowledge our ECC is the first lightweight BSD-licensed ECC for the IoT devices. We show the feasibility of our implementation by a thorough performance analysis using several implementations and optimization algorithms. Moreover, we evaluate it on a real IoT hardware platform.

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