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Publications (10 of 126) Show all publications
Dierl, S., Fiterău-Broştean, P., Howar, F., Jonsson, B., Sagonas, K. & Tåquist, F. (2026). SLλ: A Scalable Algorithm for Register Automata Learning. Journal of automated reasoning, 70(2), Article ID 14.
Open this publication in new window or tab >>SLλ: A Scalable Algorithm for Register Automata Learning
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2026 (English)In: Journal of automated reasoning, ISSN 0168-7433, E-ISSN 1573-0670, Vol. 70, no 2, article id 14Article in journal (Refereed) Published
Abstract [en]

Existing active automata learning (AAL) algorithms have demonstrated their potential in capturing the behavior of complex systems (e.g., in analyzing network protocol implementations). The most widely used AAL algorithms generate finite state machine models, such as Mealy machines or deterministic finite automata. For many analysis tasks, however, it is crucial to generate richer classes of models that also show how relations between data parameters affect system behavior. Such models have shown potential to uncover critical bugs, but their learning algorithms do not scale beyond small and well curated experiments. In this article, we present SLλ, an effective and scalable register automata (RA) learning algorithm that significantly reduces the number of membership queries required for inferring models. It achieves this by combining a tree-based cost-efficient data structure with mechanisms for computing short and restricted tests. We prove that SLλ is guaranteed to learn an acceptor, in the form of a register automaton with n locations and t transitions, for a given data language of finite index, and that it can do so with at most O(t2(2n)n+mt2mm) membership queries and O(t) equivalence queries, where m is the length of the longest counterexample received during learning. We have implemented SLλ as a new algorithm in RALib. We evaluate its performance by comparing it against SL∗, the current state-of-the-art RA learning algorithm. Experiments on a series of benchmarks show that it reduces the number of membership queries by up to an order of magnitude, and also shows substantial asymptotic improvements in bigger systems. 

Place, publisher, year, edition, pages
Springer, 2026
Keywords
Active automata learning, Register automata, Model learning.
National Category
Computer Sciences Computer Systems
Identifiers
urn:nbn:se:uu:diva-595816 (URN)10.1007/s10817-026-09758-9 (DOI)001838692000001 ()2-s2.0-105046377058 (Scopus ID)
Available from: 2026-08-19 Created: 2026-08-19 Last updated: 2026-08-19Bibliographically approved
Jonsson, B., Lång, M. & Sagonas, K. (2025). Awaiting for Godot: stateless model checking that avoids executions where nothing happens. Formal methods in system design, 67(1), 71-105
Open this publication in new window or tab >>Awaiting for Godot: stateless model checking that avoids executions where nothing happens
2025 (English)In: Formal methods in system design, ISSN 0925-9856, E-ISSN 1572-8102, Vol. 67, no 1, p. 71-105Article in journal (Refereed) Published
Abstract [en]

Stateless Model Checking (SMC) is a verification technique for concurrent programs that checks for safety violations by exploring all possible thread schedulings. It is highly effective when coupled with Dynamic Partial Order Reduction (DPOR), which introduces an equivalence on schedulings and allows SMC to explore only one execution per equivalence class. Even with DPOR, SMC often spends unnecessary effort in exploring loop iterations that are pure, i.e., have no effect on the program state. In this article, we present techniques for making SMC with DPOR more effective on programs with pure loop iterations. The first technique is a static program analysis to detect loop purity and an associated program transformation, called Partial Loop Purity Elimination, that inserts assume statements to block pure loop iterations. Subsequently, some of these assume statements are turned into await statements that completely remove many assume-blocked executions. Finally, we present an extension of the standard DPOR equivalence, obtained by weakening the conflict relation between events. All these techniques are incorporated into a new DPOR algorithm, Optimal-DPOR-Await, which can handle both await statements and the weaker conflict relation, is optimal in the sense that it explores exactly one execution in each equivalence class, and can also diagnose livelocks. Our implementation in Nidhugg shows that these techniques can significantly speed up the analysis of concurrent programs that are currently challenging for SMC tools, both for exploring their complete set of interleavings, but even for detecting concurrency errors in them.

Place, publisher, year, edition, pages
Springer, 2025
National Category
Computer Sciences
Identifiers
urn:nbn:se:uu:diva-574019 (URN)10.1007/s10703-025-00479-0 (DOI)001536014100001 ()
Funder
Swedish Research CouncilSwedish Foundation for Strategic Research
Available from: 2026-01-08 Created: 2026-01-08 Last updated: 2026-01-08Bibliographically approved
Abdulla, P., Grahn, S., Jonsson, B., Krishna, S. & Mishra, O. S. (2025). Efficient Linearizability Monitoring. Proceedings of the ACM on Programming Languages, 9(PLDI), 1937-1960
Open this publication in new window or tab >>Efficient Linearizability Monitoring
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2025 (English)In: Proceedings of the ACM on Programming Languages, E-ISSN 2475-1421, Vol. 9, no PLDI, p. 1937-1960Article in journal (Refereed) Published
Abstract [en]

This paper revisits the fundamental problem of monitoring the linearizability of concurrent stacks, queues, sets, and multisets.

Given a history of a library implementing one of these abstract data types, the monitoring problem is to answer whether the given history is linearizable.

For stacks, queues, and (multi)sets, we present monitoring algorithms with complexities (n2), (n log n), and (n), respectively, where n is the number of operations in the input history.

For stacks and queues, our results hold under the standard assumption of data-independence, i.e., the behavior of the library is not sensitive to the actual values stored in the data structure.

Past works to solve the same problems have cubic time complexity and (more seriously) have correctness issues: they either (i) lack correctness proofs or (ii) have unsound correctness proofs (we present counter-examples of the correctness proofs), or (iii) have unsound algorithms.

Our improved complexity results rely on substantially different algorithms for which we provide detailed proofs of correctness.

We have implemented our stack and queue algorithms in LiMo (Linearizability Monitor). We evaluate LiMo and compare it with the state-of-the-art tool Violin – whose correctness proofs we have found errors in – which checks for linearizability violations. Our experimental evaluation confirms that LiMo outperforms Violin regarding both efficiency and scalability.

Place, publisher, year, edition, pages
Association for Computing Machinery (ACM), 2025
National Category
Computer and Information Sciences Formal Methods
Research subject
Computer Science
Identifiers
urn:nbn:se:uu:diva-575805 (URN)10.1145/3729328 (DOI)001638771600001 ()2-s2.0-105008274441 (Scopus ID)
Available from: 2026-01-13 Created: 2026-01-13 Last updated: 2026-04-02Bibliographically approved
Graf, S., Jonsson, B., Khodabandeloo, B., Huang, C., Huber, N., Rümmer, P. & Wang, Y. (2025). Timing is All You Need. In: Mike Hinchey; Bernhard Steffen (Ed.), The Combined Power of Research, Education, and Dissemination: Essays Dedicated to Tiziana Margaria on the Occasion of Her 60th Birthday (pp. 259-279). Cham: Springer
Open this publication in new window or tab >>Timing is All You Need
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2025 (English)In: The Combined Power of Research, Education, and Dissemination: Essays Dedicated to Tiziana Margaria on the Occasion of Her 60th Birthday / [ed] Mike Hinchey; Bernhard Steffen, Cham: Springer, 2025, p. 259-279Chapter in book (Refereed)
Abstract [en]

Deterministic models play a crucial role in computer system development, enabling the simulation and verification of system behaviors before ModelDriven Development (MDD) tools transform and compile these models into final implementations. Ensuring determinism is essential to guarantee that the behaviors of the implemented system maintain the properties analyzed in the models.

This paper investigates the semantics of deterministic models for data-flow networks, where systems consist of components that compute functions on streams. While Kahn Process Networks (KPN) serve as a well-established semantic theory for time-insensitive deterministic systems, it proves inadequate for systems with time dependent components. To address this limitation, we use the concept of timed streams and develop a fixed-point theory tailored for time-sensitive systems in the style of KPN. This theory serves as the foundation for the MDD tool-chain, known as MIMOS, currently under development in Uppsala.

Place, publisher, year, edition, pages
Cham: Springer, 2025
Series
Lecture Notes in Computer Science, ISSN 0302-9743, E-ISSN 1611-3349 ; 15240
National Category
Computer Sciences Control Engineering
Identifiers
urn:nbn:se:uu:diva-557532 (URN)10.1007/978-3-031-73887-6_18 (DOI)001400883300018 ()2-s2.0-85208072715 (Scopus ID)978-3-031-73886-9 (ISBN)978-3-031-73887-6 (ISBN)
Available from: 2025-05-28 Created: 2025-05-28 Last updated: 2025-05-28Bibliographically approved
Asadian, H., Fiterau-Brostean, P., Jonsson, B. & Sagonas, K. (2024). Monitor-based Testing of Network Protocol Implementations Using Symbolic Execution. In: 19TH INTERNATIONAL CONFERENCE ON AVAILABILITY, RELIABILITY, AND SECURITY, ARES 2024: . Paper presented at 19th International Conference on Availability, Reliability, and Security (ARES), JUL 30-AUG 02, 2024, Vienna, AUSTRIA. Association for Computing Machinery (ACM), Article ID 17.
Open this publication in new window or tab >>Monitor-based Testing of Network Protocol Implementations Using Symbolic Execution
2024 (English)In: 19TH INTERNATIONAL CONFERENCE ON AVAILABILITY, RELIABILITY, AND SECURITY, ARES 2024, Association for Computing Machinery (ACM), 2024, article id 17Conference paper, Published paper (Refereed)
Abstract [en]

Implementations of network protocols must conform to their specifications in order to avoid security vulnerabilities and interoperability issues. To detect errors, testing must investigate an implementation's response to a wide range of inputs, including those that could be supplied by an attacker. This can be achieved by symbolic execution, but its application in testing network protocol implementations has so far been limited. One difficulty when testing such implementations is that the inputs and requirements for processing a packet depend on the sequence of previous packets. We present a novel technique to encode protocol requirements by monitors, and then employ symbolic execution to detect violations of these requirements in protocol implementations. A monitor is a component external to the SUT, that observes a sequence of packets exchanged between protocol parties, maintains information about the state of the interaction, and can thereby detect requirement violations. Using monitors, requirements for stateful network protocols can be tested with a wide variety of inputs, without intrusive modifications in the source code of the SUT. We have applied our technique on the most recent versions of several widely-used DTLS and QUIC protocol implementations, and have been able to detect twenty two previously unknown bugs in them, twenty one of which have already been fixed and the remaining one has been confirmed.

Place, publisher, year, edition, pages
Association for Computing Machinery (ACM), 2024
Keywords
Software security, security testing, network security, network protocols, symbolic execution, monitors, DTLS, QUIC
National Category
Computer Sciences
Identifiers
urn:nbn:se:uu:diva-548995 (URN)10.1145/3664476.3664521 (DOI)001283894700044 ()2-s2.0-85200367471 (Scopus ID)979-8-4007-1718-5 (ISBN)
Conference
19th International Conference on Availability, Reliability, and Security (ARES), JUL 30-AUG 02, 2024, Vienna, AUSTRIA
Funder
Swedish Foundation for Strategic ResearchSwedish Research Council
Available from: 2025-01-31 Created: 2025-01-31 Last updated: 2026-01-29Bibliographically approved
Abdulla, P., Atig, M. F., Das, S., Jonsson, B. & Sagonas, K. (2024). Parsimonious Optimal Dynamic Partial Order Reduction. In: Ganesh, V Gurfinkel, A (Ed.), Computer Aided Verification, PT II, CAV 2024: . Paper presented at 36th International Conference on Computer-Aided Verification (CAV), JUN 24-27, 2024, Montreal, CANADA (pp. 19-43). Springer Publishing Company, 14682
Open this publication in new window or tab >>Parsimonious Optimal Dynamic Partial Order Reduction
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2024 (English)In: Computer Aided Verification, PT II, CAV 2024 / [ed] Ganesh, V Gurfinkel, A, Springer Publishing Company, 2024, Vol. 14682, p. 19-43Conference paper, Published paper (Refereed)
Abstract [en]

Statelessmodel checking is a fully automatic verification technique for concurrent programs that checks for safety violations by exploring all possible thread schedulings. It becomes effective when coupled with Dynamic Partial Order Reduction (DPOR), which introduces an equivalence on schedulings and reduces the amount of needed exploration. DPOR algorithms that are optimal are particularly effective in that they guarantee to explore exactly one execution from each equivalence class. Unfortunately, existing sequence-based optimal algorithms may in the worst case consume memory that is exponential in the size of the analyzed program. In this paper, we present Parsimonious-OPtimal DPOR (POP), an optimal DPOR algorithm for analyzing multi-threaded programs under sequential consistency, whose space consumption is polynomial in the worst case. POP combines several novel algorithmic techniques, including (i) a parsimonious race reversal strategy, which avoids multiple reversals of the same race, (ii) an eager race reversal strategy to avoid storing initial fragments of to-be-explored executions, and (iii) a space-efficient scheme for preventing redundant exploration, which replaces the use of sleep sets. Our implementation in Nidhugg shows that these techniques can significantly speed up the analysis of concurrent programs, and do so with low memory consumption. Comparison to TruSt, a related optimal DPOR algorithm that represents executions as graphs, shows that POP's implementation achieves similar performance for smaller benchmarks, and scales much better than TruSt's on programs with long executions.

Place, publisher, year, edition, pages
Springer Publishing Company, 2024
Series
Lecture Notes in Computer Science, ISSN 0302-9743, E-ISSN 1611-3349
National Category
Computer Sciences
Identifiers
urn:nbn:se:uu:diva-540574 (URN)10.1007/978-3-031-65630-9_2 (DOI)001307890400002 ()2-s2.0-85200666835 (Scopus ID)978-3-031-65629-3 (ISBN)978-3-031-65630-9 (ISBN)
Conference
36th International Conference on Computer-Aided Verification (CAV), JUN 24-27, 2024, Montreal, CANADA
Funder
Swedish Research CouncilSwedish Foundation for Strategic Research
Available from: 2024-10-17 Created: 2024-10-17 Last updated: 2026-06-01Bibliographically approved
Dierl, S., Fiterau-Brostean, P., Howar, F., Jonsson, B., Sagonas, K. & Tåquist, F. (2024). Scalable Tree-based Register Automata Learning. In: Bernd Finkbeiner; Laura Kovács (Ed.), Tools and Algorithms for the Construction and Analysis of Systems: 30th International Conference, TACAS 2024, Held as Part of the European Joint Conferences on Theory and Practice of Software, ETAPS 2024, Luxembourg City, Luxembourg, April 6–11, 2024, Proceedings, Part II. Paper presented at 30th International Conference on Tools and Algorithms for the Construction and Analysis of Systems (TACAS) Held as Part of the 27th European Joint Conferences on Theory and Practice of Software (ETAPS), April 6-11, 2024, Luxembourg, Luxembourg (pp. 87-108). Cham: Springer
Open this publication in new window or tab >>Scalable Tree-based Register Automata Learning
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2024 (English)In: Tools and Algorithms for the Construction and Analysis of Systems: 30th International Conference, TACAS 2024, Held as Part of the European Joint Conferences on Theory and Practice of Software, ETAPS 2024, Luxembourg City, Luxembourg, April 6–11, 2024, Proceedings, Part II / [ed] Bernd Finkbeiner; Laura Kovács, Cham: Springer, 2024, p. 87-108Conference paper, Published paper (Refereed)
Abstract [en]

Existing active automata learning (AAL) algorithms have demonstrated their potential in capturing the behavior of complex systems (e.g., in analyzing network protocol implementations). The most widely used AAL algorithms generate finite state machine models, such as Mealy machines. For many analysis tasks, however, it is crucial to generate richer classes of models that also show how relations between data parameters affect system behavior. Such models have shown potential to uncover critical bugs, but their learning algorithms do not scale beyond small and well curated experiments. In this paper, we present SLλ, an effective and scalable register automata (RA) learning algorithm that significantly reduces the number of tests required for inferring models. It achieves this by combining a tree-based cost-efficient data structure with mechanisms for computing short and restricted tests. We have implemented SLλ as a new algorithm in RALib. We evaluate its performance by comparing it against SL*, the current state-of-the-art RA learning algorithm, in a series of experiments, and show superior performance and substantial asymptotic improvements in bigger systems.

Place, publisher, year, edition, pages
Cham: Springer, 2024
Series
Lecture Notes in Computer Science, ISSN 0302-9743, E-ISSN 1611-3349 ; 14571
Keywords
Active automata learning, Register automata
National Category
Computer Sciences Computer Systems
Identifiers
urn:nbn:se:uu:diva-538995 (URN)10.1007/978-3-031-57249-4_5 (DOI)001284179800005 ()978-3-031-57248-7 (ISBN)978-3-031-57249-4 (ISBN)
Conference
30th International Conference on Tools and Algorithms for the Construction and Analysis of Systems (TACAS) Held as Part of the 27th European Joint Conferences on Theory and Practice of Software (ETAPS), April 6-11, 2024, Luxembourg, Luxembourg
Funder
Swedish Research CouncilSwedish Foundation for Strategic ResearchKnut and Alice Wallenberg FoundationGerman Research Foundation (DFG), 495857894German Research Foundation (DFG), 442146713
Available from: 2024-09-24 Created: 2024-09-24 Last updated: 2024-09-24Bibliographically approved
Fiterau-Brostean, P., Jonsson, B., Sagonas, K. & Tåquist, F. (2024). SMBugFinder: An Automated Framework for Testing Protocol Implementations for State Machine Bugs. In: Christakis, M Pradel, M (Ed.), PROCEEDINGS OF THE 33RD ACM SIGSOFT INTERNATIONAL SYMPOSIUM ON SOFTWARE TESTING AND ANALYSIS, ISSTA 2024: . Paper presented at 33rd ACM SIGSOFT International Conference on Software Testing and Analysis (ISSTA), SEP 16-20, 2024, Vienna, AUSTRIA (pp. 1866-1870). Association for Computing Machinery (ACM)
Open this publication in new window or tab >>SMBugFinder: An Automated Framework for Testing Protocol Implementations for State Machine Bugs
2024 (English)In: PROCEEDINGS OF THE 33RD ACM SIGSOFT INTERNATIONAL SYMPOSIUM ON SOFTWARE TESTING AND ANALYSIS, ISSTA 2024 / [ed] Christakis, M Pradel, M, Association for Computing Machinery (ACM), 2024, p. 1866-1870Conference paper, Published paper (Refereed)
Abstract [en]

Implementations of stateful network protocols must keep track of the presence, order and type of exchanged messages. Any errors, socalled state machine bugs, can compromise security. SMBugFinder provides an automated framework for detecting these bugs in network protocol implementations using black-box testing. It takes as input a state machine model of the protocol implementation which is tested and a catalogue of bug patterns for the protocol conveniently specified as finite automata. It then produces sequences that expose the catalogued bugs in the tested implementation. Connection to a harness allows SMBugFinder to validate these sequences. The technique behind SMbugFinder has been evaluated successfully on DTLS and SSH in prior work. In this paper, we provide a user-level view of the tool using the EDHOC protocol as an example.

Place, publisher, year, edition, pages
Association for Computing Machinery (ACM), 2024
Keywords
Software security, protocol security, network protocols, protocol state fuzzing, model-based testing, model checking
National Category
Computer Systems Embedded Systems
Identifiers
urn:nbn:se:uu:diva-546277 (URN)10.1145/3650212.3685310 (DOI)001324606300155 ()2-s2.0-85205574671 (Scopus ID)979-8-4007-0612-7 (ISBN)
Conference
33rd ACM SIGSOFT International Conference on Software Testing and Analysis (ISSTA), SEP 16-20, 2024, Vienna, AUSTRIA
Funder
Swedish Research CouncilSwedish Foundation for Strategic ResearchKnut and Alice Wallenberg Foundation
Available from: 2025-01-08 Created: 2025-01-08 Last updated: 2025-01-08Bibliographically approved
Asadian, H., Fiterău-Broştean, P., Jonsson, B. & Sagonas, K. (2024). Testing IoT Protocol Requirements Using Fuzzing and Symbolic Execution: Application to CoAP. In: 2024 IEEE Conference on Standards for Communications and Networking (CSCN): . Paper presented at 2024 Conference on Standards for Communications and Networking, Nov 25-27, 2024, Serbia (pp. 48-54). Institute of Electrical and Electronics Engineers (IEEE)
Open this publication in new window or tab >>Testing IoT Protocol Requirements Using Fuzzing and Symbolic Execution: Application to CoAP
2024 (English)In: 2024 IEEE Conference on Standards for Communications and Networking (CSCN), Institute of Electrical and Electronics Engineers (IEEE), 2024, p. 48-54Conference paper, Published paper (Refereed)
Abstract [en]

The rapid expansion of the Internet of Things (IoT) has introduced the need for thorough testing of its protocol implementations to ensure conformance to their specifications and increase their security. This paper investigates the application of two of the major testing techniques, fuzz testing and symbolic execution, to test the implementations of the Constrained Application Protocol (CoAP), a key protocol in the IoT ecosystem. We explore the efficacy of these techniques in discovering requirement violations in CoAP implementations. Focusing on two widely-used CoAP implementations, libcoap and FreeCoAP, we systematically apply both fuzzing and symbolic execution to test conformance with key requirements derived from CoAP's specifications. Our findings demonstrate the strengths and limitations of both approaches, and highlight nine nonconformances in these implementations, most of which have been fixed. Finally, we provide insights into how fuzzing and symbolic execution can be effectively utilized for protocol testing.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2024
Series
IEEE Conference on Standards for Communications and Networking, ISSN 2644-3244, E-ISSN 2644-3252
National Category
Computer Sciences
Identifiers
urn:nbn:se:uu:diva-557897 (URN)10.1109/CSCN63874.2024.10849709 (DOI)001442211400009 ()2-s2.0-85218179930 (Scopus ID)979-8-3315-0743-5 (ISBN)979-8-3315-0742-8 (ISBN)
Conference
2024 Conference on Standards for Communications and Networking, Nov 25-27, 2024, Serbia
Funder
Swedish Foundation for Strategic Research, aSSIsTSwedish Research Council
Available from: 2025-06-03 Created: 2025-06-03 Last updated: 2026-01-29Bibliographically approved
Abdulla, P., Atig, M. F., Das, S., Jonsson, B. & Sagonas, K. (2024). Trading Space for Simplicity in Stateless Model Checking. In: Susanne Graf; Paul Pettersson; Bernhard Steffen (Ed.), Real Time and Such: Essays Dedicated to Wang Yi to Celebrate His Scientific Career. Paper presented at Real Time and Such: Essays Dedicated to Wang Yi to Celebrate His Scientific Career (pp. 79-97). Paper presented at Real Time and Such: Essays Dedicated to Wang Yi to Celebrate His Scientific Career. Springer
Open this publication in new window or tab >>Trading Space for Simplicity in Stateless Model Checking
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2024 (English)In: Real Time and Such: Essays Dedicated to Wang Yi to Celebrate His Scientific Career / [ed] Susanne Graf; Paul Pettersson; Bernhard Steffen, Springer, 2024, p. 79-97Chapter in book (Refereed)
Abstract [en]

Stateless model checking is a fully automatic verification technique for concurrent programs, which checks for safety violations by exploring all possible thread schedulings. It becomes effective when coupled with Dynamic Partial Order Reduction (DPOR), which introduces an equivalence on schedulings and reduces the amount of exploration. DPOR algorithms that are optimal are particularly effective in that they guarantee to explore exactly one execution from each equivalence class. Recently, the authors of this paper presented Parsimonious-OPtimal (POP) DPOR, an optimal DPOR algorithm for analyzing multi-threaded programs under sequential consistency, whose space consumption is polynomial in the worst case. This space consumption bound was realized due to a carefully crafted encoding of so-called sleep sets, a mechanism for preventing redundant exploration. This encoding brings some conceptual complexity to POP, which achieves good worst-case performance at the possible expense of worse average-case performance. In this paper, we present a simpler technique for managing sleep sets, which has exponential worst-case space consumption but better average-case performance. We experimentally compare these two sleep set management schemes on a range of benchmarks. The experimental results confirm that a simpler sleep set is a better choice when designing DPOR algorithms as they are faster and have similar memory consumption for average programs.

Place, publisher, year, edition, pages
Springer, 2024
Series
Lecture Notes in Computer Science, ISSN 0302-9743, E-ISSN 1611-3349 ; 15230
Keywords
Stateless Model Checking, Model Checking, DPOR, Concurrent Programs, Multi-threaded programs
National Category
Computer Sciences
Identifiers
urn:nbn:se:uu:diva-551542 (URN)10.1007/978-3-031-73751-0_8 (DOI)001400370700009 ()2-s2.0-85208017586 (Scopus ID)9783031737503 (ISBN)9783031737510 (ISBN)
Conference
Real Time and Such: Essays Dedicated to Wang Yi to Celebrate His Scientific Career
Funder
Swedish Foundation for Strategic ResearchSwedish Research Council
Available from: 2025-02-25 Created: 2025-02-25 Last updated: 2025-03-11Bibliographically approved
Projects
Model Generation and Testing through Automata Learning [2011-06167_VR]; Uppsala UniversityDevelopment of Scalable and Correct Concurrent Data Structures: Techniques and Tools [2015-05417_VR]; Uppsala UniversitySystematic, Efficient, and Scalable Automated Testing for Concurrent Software [2019-05466_VR]; Uppsala University; Publications
Jonsson, B., Lång, M. & Sagonas, K. (2025). Awaiting for Godot: stateless model checking that avoids executions where nothing happens. Formal methods in system design, 67(1), 71-105Abdulla, P., Atig, M. F., Meyer Bønneland, F., Das, S., Jonsson, B., Lång, M. & Sagonas, K. (2023). Tailoring Stateless Model Checking for Event-Driven Multi-threaded Programs. In: Étienne André; Jun Sun (Ed.), Automated Technology for Verification and Analysis: 21st International Symposium, ATVA 2023, Singapore, October 24–27, 2023, Proceedings, Part II. Paper presented at 21st International Symposium, ATVA 2023, Singapore, October 24–27, 2023 (pp. 176-198). Cham: Springer
Effective Security Testing of Network Protocol Implementations [2023-05363_VR]; Uppsala University; Publications
Sagonas, K. & Typaldos, T. (2026). PSF: A Generic and Extensible Framework for Protocol State Fuzzing. In: Eva Darulova; Anthony W. Lin; Philipp Rümmer (Ed.), Computer Aided Verification: 38th International Conference, CAV 2026, Lisbon, Portugal, July 26–29, 2026, Proceedings, Part I. Paper presented at 38th International Conference on Computer Aided Verification - CAV-Annual, July 26-29, 2026, Lisbon, Portugal (pp. 167-180). Cham: SpringerJonsson, B., Lång, M. & Sagonas, K. (2025). Awaiting for Godot: stateless model checking that avoids executions where nothing happens. Formal methods in system design, 67(1), 71-105Chen, N., Fiterău-Broştean, P. & Sagonas, K. (2025). State Fuzzing DTLS 1.3 Implementations. In: 2025 IEEE Conference on Standards for Communications and Networking (CSCN): . Paper presented at IEEE Conference on Standards for Communications and Networking (CSCN 2025), Bologna, Italy, 15-17 September, 2025 (pp. 426-432). Institute of Electrical and Electronics Engineers (IEEE)
MCSE: Model-Constructing Symbolic Execution for Web Security [2025-06185_VR]; Uppsala University; Publications
Esen, Z., Rümmer, P. & Weber, T. (2026). Sound and Complete Invariant-Based Heap Encodings. Paper presented at OOPSLA, Oakland, CA, USA, October, 2026. Proceedings of the ACM on Programming Languages, 10(OOPSLA1), 794-822, Article ID 120.
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ORCID iD: ORCID iD iconorcid.org/0000-0001-7897-601X

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