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With increasingly irregular memory access patterns in Indirect Memory Access (IMA) and Graph Processing (GP) applications, Virtual Address Translation (VAT) not only has become a major performance bottleneck, but also a key contributor to high power consumption in out-of-order (OoO) multi-core processor pipeline. We find that this problem can be attributed to a large extent to an inefficient utilization of TLBs in pointer-chasing instructions (i.e. load-to-load), which constitute a significant portion of workloads in IMA/GP. Conventionally, VATs for pointer-chasing are performed via a series of TLB look-ups: one for each load in the pointer chain. However, this approach is sub-optimal as it overlooks the correlations between pointers, missing opportunities to perform VATs through more costeffective calculations instead of relying on the more expensive TLB look-ups. This work draws on the insight that in pointer-chasing workloads, the physical page holding an upstream pointer is often at a fixed distance to the physical page where a downstream pointer resides. Building on this insight, we introduce RefleXive address Translation (RXT), which encodes the physical page distance (termed PageDist) between an upstream and downstream pointer into the unused upper 16 bits of the upstream pointer's virtual address. Consequently, RXT can compute the translation of a pointer by directly adding the PageDist to its residing address (the physical address where the pointer is stored). This process can be recursively applied throughout the pointer-chasing sequence, transforming address translation from a sequence of TLB accesses to computes. Through gem5 full-system simulation, RXT reduces TLB energy consumption for pointer-chasing applications by an average of 41.48 % (up to 62.50 %) and decreases overall core power density by 4.65 % (up to 13.09 %), without compromising application execution time. In fact, RXT even improves program runtime by an average of 0.71 % (up to 2.09 %).

We introduce the fake-busy and true-idle problems encountered when running large graph workloads on chipletbased Out-of-Order (OoO) multi-cores. Caused by high interchiplet communication latency and irregular memory access patterns, these issues lead to inefficient use of core pipeline resources such as the Reorder Buffer (RoB) and Load Queue (LQ). Our evaluation shows that reducing RoB and LQ sizes has minimal impact on application performance, revealing new performance optimization opportunities for large graph workloads.

Graph applications, characterized by irregular memory footprints and low branch prediction accuracy, pose significant challenges for modern computing systems. This work examines the performance of state-of-the-art chiplet-based multi-core architectures featuring out-of-order (OoO) cores with deep pipeline components, such as reorder buffers (ROB) and load queues (LQ), when executing graph workloads.Through detailed micro-architectural profiling, we find that OoO cores are often inefficiently utilized. We identify two dominant causes: fake-busy and true-idle. In fake-busy, a core waiting for a branch-resolving load speculatively skips the current branch, enters the next loop, and repeats this process— iteratively issuing a cascade of speculative instructions. In true-idle, a core waiting for a branch-resolving load speculatively executes code of the current branch, where instructions often depend on the branch-resolving load itself, resulting in unproductive pipeline stalls and instructions accumulating in the ROB. Due to high load latency in chiplet architectures and low branch prediction accuracy typical of graph workloads, both scenarios suffer from deep speculation and frequent pipeline squashing, leading to inefficient utilization of OoO pipeline resources.Our results show that halving the ROB and LQ sizes leads to only minor performance degradation—average slowdowns of 4.3% and 1.0%, respectively—across most applications, with the exception of two cases that exhibit more substantial slowdowns of 37.3% (half-ROB) and 5.6% (half-LQ). Moreover, operating at a lower core frequency (e.g., 2.0 GHz) yields an energy-delay product (EDP) comparable to that of higher frequencies (e.g., 2.5 GHz and 3.0 GHz) across all applications. Together, these findings highlight new opportunities for performance and power co-optimization when running graph workloads on chiplet-based multi-core systems.