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With increasingly irregular memory access patterns in Indirect Memory Access (IMA) and Graph Processing (GP) applications, Virtual Address Translation (VAT) not only has become a major performance bottleneck, but also a key contributor to high power consumption in out-of-order (OoO) multi-core processor pipeline. We find that this problem can be attributed to a large extent to an inefficient utilization of TLBs in pointer-chasing instructions (i.e. load-to-load), which constitute a significant portion of workloads in IMA/GP. Conventionally, VATs for pointer-chasing are performed via a series of TLB look-ups: one for each load in the pointer chain. However, this approach is sub-optimal as it overlooks the correlations between pointers, missing opportunities to perform VATs through more costeffective calculations instead of relying on the more expensive TLB look-ups. This work draws on the insight that in pointer-chasing workloads, the physical page holding an upstream pointer is often at a fixed distance to the physical page where a downstream pointer resides. Building on this insight, we introduce RefleXive address Translation (RXT), which encodes the physical page distance (termed PageDist) between an upstream and downstream pointer into the unused upper 16 bits of the upstream pointer's virtual address. Consequently, RXT can compute the translation of a pointer by directly adding the PageDist to its residing address (the physical address where the pointer is stored). This process can be recursively applied throughout the pointer-chasing sequence, transforming address translation from a sequence of TLB accesses to computes. Through gem5 full-system simulation, RXT reduces TLB energy consumption for pointer-chasing applications by an average of 41.48 % (up to 62.50 %) and decreases overall core power density by 4.65 % (up to 13.09 %), without compromising application execution time. In fact, RXT even improves program runtime by an average of 0.71 % (up to 2.09 %).

We introduce the fake-busy and true-idle problems encountered when running large graph workloads on chipletbased Out-of-Order (OoO) multi-cores. Caused by high interchiplet communication latency and irregular memory access patterns, these issues lead to inefficient use of core pipeline resources such as the Reorder Buffer (RoB) and Load Queue (LQ). Our evaluation shows that reducing RoB and LQ sizes has minimal impact on application performance, revealing new performance optimization opportunities for large graph workloads.

Graph applications, characterized by irregular memory footprints and low branch prediction accuracy, pose significant challenges for modern computing systems. This work examines the performance of state-of-the-art chiplet-based multi-core architectures featuring out-of-order (OoO) cores with deep pipeline components, such as reorder buffers (ROB) and load queues (LQ), when executing graph workloads.Through detailed micro-architectural profiling, we find that OoO cores are often inefficiently utilized. We identify two dominant causes: fake-busy and true-idle. In fake-busy, a core waiting for a branch-resolving load speculatively skips the current branch, enters the next loop, and repeats this process— iteratively issuing a cascade of speculative instructions. In true-idle, a core waiting for a branch-resolving load speculatively executes code of the current branch, where instructions often depend on the branch-resolving load itself, resulting in unproductive pipeline stalls and instructions accumulating in the ROB. Due to high load latency in chiplet architectures and low branch prediction accuracy typical of graph workloads, both scenarios suffer from deep speculation and frequent pipeline squashing, leading to inefficient utilization of OoO pipeline resources.Our results show that halving the ROB and LQ sizes leads to only minor performance degradation—average slowdowns of 4.3% and 1.0%, respectively—across most applications, with the exception of two cases that exhibit more substantial slowdowns of 37.3% (half-ROB) and 5.6% (half-LQ). Moreover, operating at a lower core frequency (e.g., 2.0 GHz) yields an energy-delay product (EDP) comparable to that of higher frequencies (e.g., 2.5 GHz and 3.0 GHz) across all applications. Together, these findings highlight new opportunities for performance and power co-optimization when running graph workloads on chiplet-based multi-core systems.

We present TaDA, a system architecture enabling efficient execution of Internet of Things (IoT) applications across multiple computing units, powered by ambient energy harvesting. Low-power microcontroller units (MCUs) are increasingly specialized; for example, custom designs feature hardware acceleration of neural network inference, next to designs providing energy-efficient input/output. As application requirements are growingly diverse, we argue that no single MCU can efficiently fulfill them. TaDA allows programmers to assign the execution of different slices of the application logic to the most efficient MCU for the job. We achieve this by decoupling task executions in time and space, using a special-purpose hardware interconnect we design, while providing persistent storage to cross periods of energy unavailability. We compare our prototype performance against the single most efficient computing unit for a given workload. We show that our prototype saves up to 96.7% energy per application round. Given the same energy budget, this yields up to a 68.7x throughput improvement.

We propose a novel technique which exploits the concept of Game-of-Life (GoL) originated from cellular automata to achieve a light-weight yet effective temperature-aware DVFS for tile-based Chip Many-Core Processors (CMPs). The proposed DVFS mechanism is based on the strategy that a CMP V/F region, consisting of several tiles sharing the same V/F level, first determines the local V/F level according to core and uncore performance interests of the resident tiles. Then, based on the temperatures of both local and neighbor V/F regions, the performance based V/F policy is revised towards thermal safety, minimizing the occurrence of chip thermal urgency threshold (TUT) violation. As such, our temperature-aware DVFS strategy implements an ecosystem where V/F regions try to secure as much performance as possible, but a sustainable thermal environment for itself and neighbor regions is also maintained, essentially mimicking the behavior of living cells that co-exist harmonically in a common environment. Full-system evaluations with PARSEC and SPEC OMP2012 multi-threaded benchmarks show that our GoL based temperature-aware DVFS technique can averagely reduce TUT violation by 43.4% (59.5% in maximum) compared to a thermal-oblivious DVFS mechanism and by 20.7% (31.9% in maximum) compared to a local-temperature aware DVFS mechanism, with graceful performance degradation.

CNNs are difficult to achieve inter-layer parallelism because of the data dependence between layers. In the paper, we propose Symbolic-Execution CNN (SE-CNN), which breaks data dependence between CNN layers via value prediction. Our insight is that in post-trained CNNs, only a subset (less than 10%) of neurons are activated (producing non-zero values) to identify patterns in inputs while most of the other neurons remain silent (producing zeros). This is because given an input image there are only a limited number of features presented. Thus, within the CNN, the neurons that are sensitive to the given features are more exercised than the others. Based on this insight, SE-CNN works in two successive phases: A parallel computation phase and a serial correction phase. In the parallel computation phase, each CNN layer starts computation simultaneously based on predicted inputs: we predict most of the neurons having zeros as inputs. For non-zero input neurons we predict their inputs for the next input image the same as the previous ones. In the serial correction phase, each layer compares the predicted inputs with the real ones to correct its computation results if necessary. If a neuron has predicted correctly its input during the parallel phase, thus the corresponding neuron passes its serial phase. Otherwise the neuron will amend its prediction with a light-weight result amendment mechanism based on the real inputs. We imple-ment SE-CNN on top of the streaming processor of a state-of-the-art general purpose GPU (GPGPU) architecture, adding marginal hardware overheads in area and power consumption. We also provide application programming interfaces (APIs) so that CNNs that have already been implemented can directly enjoy the benefits of our technique. We utilize GPGPU-sim as our experimental platform, benchmarked with 9 well-accepted CNNs from recent years' ILSVRC contests. Experimental results show that compared to other three state-of-the-art GPU based CNN acceleration mechanisms, SE-CNN can averagely achieve 13.4x, 10.4x and 7.9x (maximally 22.0x, 18.7x and 16.4x) CNN execution speedup while maintaining over 95% of classification accuracy.

We present experimental results investigating the use of silent stores in the battery-less Internet of Things (IoT). Silent stores occur in a program when the value being written onto memory exactly matches the memory content; general-purpose computing systems exploit silent stores to improve memory throughput. Battery-less IoT devices, on the other hand, rely on ambient energy harvesting as the only power source. Erratic energy patterns, however, cause frequent power failures, rendering executions intermittent and thereby requiring the use of energy-hungry non-volatile memory (NVM) to persist program states. The question we seek to answer is whether intermittently-computing IoT devices may reap any benefit from silent stores – or from a related variation called temporary silent store – as a way to save energy by sparing NVM operations. Our results point to a negative answer. Albeit in principle we observe copious (temporary) silent stores in staple battery-less IoT benchmarks, resource limitations of IoT devices and the features of modern NVM technology, such as FRAM, largely neutralize their impact on the energy figures in practice. In actual executions, for example, we measure a mere 2.2% energy consumption improvement, on average. The (negative) results we present here, obtained based on common IoT architectures such as ARM Cortex M* and MSP430 microcontrollers, raise awareness on the features of battery-less IoT devices and inform future research efforts.

We propose a novel approach for hardware-based strict TSO persistency, called TSOPER. We allow a TSO persistency model to freely coalesce values in the caches, by forming atomic groups of cachelines to be persisted. A group persist is initiated for an atomic group if any of its newly written values are exposed to the outside world. A key difference with prior work is that our architecture is based on the concept of a TSO persist buffer, that sits in parallel to the shared LLC, and persists atomic groups directly from private caches to NVM, bypassing the coherence serialization of the LLC.

To impose dependencies among atomic groups that are persisted from the private caches to the TSO persist buffer, we introduce a sharing-list coherence protocol that naturally captures the order of coherence operations in its sharing lists, and thus can reconstruct the dependencies among different atomic groups entirely at the private cache level without involving the shared LLC. The combination of the sharing-list coherence and the TSO persist buffer allows persist operations and writes to non-volatile memory to happen in the background and trail the coherence operations. Coherence runs ahead at full speed; persistency follows belatedly.

Our evaluation shows that TSOPER provides the same level of reordering as a program-driven relaxed model, hence, approximately the same level of performance, albeit without needing the programmer or compiler to be concerned about false sharing, data-race-free semantics, etc., and guaranteeing all software that can run on top of TSO, automatically persists in TSO.