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Graphene, the atomically thin material of carbon atoms, first isolated experimentally in 2004, exhibits remarkable properties and holds potential for applications in quantum, electrical, and spin-based devices. The chemical vapor deposition (CVD) method enables graphene production on a large scale, merging its exceptional characteristics with scalability and high-quality implementation. Despite the extraordinary promise of CVD graphene with structural imperfections, the main challenge for graphene electronics and spintronics lies in achieving reliability at the device and circuit levels with scalable materials and interfaces. To address these, it is essential to understand the intricacies, endurance, and performance issues in graphene devices. In this thesis, to understand graphene interfaces in devices, we first explored a critical aspect of graphene's interaction with metal oxides, particularly titanium oxide (TiO_x) and aluminum oxide (AlO_x), and their implications for graphene-based nanoelectronic and spintronic devices. Investigating the electrical characteristics of graphene, both with and without oxides, uncovers the distinct behaviors of TiO_x and AlO_x when interfaced with graphene, highlighting the charge transfer-induced p-type doping and the formation of sp³ defects, traps, and impurities, especially at the AlO_x/graphene interface. These findings bring new insights for graphene spintronic devices while opening possibilities for novel functionalities such as hybrid resistive switching devices. Advancing further towards van der Waals heterostructures in these studies, we could also observe the impact of monolayer MoS₂ on graphene’s properties. Next, we explored how CVD graphene devices withstand high current stress to elucidate device durability and resilience. We examine the impact of extreme electric currents on channel structures and resistive tunnel barrier interfaces, focusing on their feasibility for high-capacity electronic and spintronic applications. Here, despite the polycrystalline nature of CVD graphene, we could observe the highest current density of 5.2×10⁸ Acm^-2 in graphene on Si/SiO₂ substrates, elevating it further to 1.7×10⁹ Acm^-2 on diamond substrates, remarkably exceeding previous reports. Performing systematic cyclic electrical measurements, with a gradual increase in the applied high current, we could determine the limits of the reversible regime for safe device operation of both channels and contacts. This knowledge of high current limits and oxide interfaces with graphene leads to an innovative current-treated passive graphene (CTPG) system, where we passivated graphene with metal oxide and applied high current to enhance quality. This method addresses the challenge of interfacial defects and remarkably improves carrier mobility, thereby reducing Coulomb scattering while mitigating electromigration issues. The CTPG presents a scalable platform for stable nanoelectronic and spintronic circuits. The experiments and systems studied in this thesis open possibilities for the exploration of temperature-dependent charge and spin transport measurements via new heterostructures and interfaces with different material combinations.